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  /src/external/gpl3/binutils/dist/gas/
scfidw2gen.h 31 void scfi_dot_cfi (int arg, unsigned reg1, unsigned reg2, offsetT offset,
scfidw2gen.c 171 scfi_dot_cfi (int arg, unsigned reg1, unsigned reg2, offsetT offset,
187 cfi_add_CFA_offset (reg1, offset);
191 cfi_add_CFA_val_offset (reg1, offset);
195 cfi_add_CFA_offset (reg1,
200 cfi_add_CFA_def_cfa (reg1, offset);
204 cfi_add_CFA_register (reg1, reg2);
208 cfi_add_CFA_def_cfa_register (reg1);
221 cfi_add_CFA_restore (reg1);
244 reg1 = cfi_parse_reg ();
245 cfi_add_CFA_undefined (reg1);
    [all...]
  /src/external/gpl3/binutils.old/dist/gas/
scfidw2gen.h 31 void scfi_dot_cfi (int arg, unsigned reg1, unsigned reg2, offsetT offset,
scfidw2gen.c 171 scfi_dot_cfi (int arg, unsigned reg1, unsigned reg2, offsetT offset,
187 cfi_add_CFA_offset (reg1, offset);
191 cfi_add_CFA_val_offset (reg1, offset);
195 cfi_add_CFA_offset (reg1,
200 cfi_add_CFA_def_cfa (reg1, offset);
204 cfi_add_CFA_register (reg1, reg2);
208 cfi_add_CFA_def_cfa_register (reg1);
221 cfi_add_CFA_restore (reg1);
244 reg1 = cfi_parse_reg ();
245 cfi_add_CFA_undefined (reg1);
    [all...]
  /src/sys/arch/powerpc/pci/
pchb.c 80 pcireg_t reg1, reg2; local
83 reg1 = pci_conf_read(pa->pa_pc, pa->pa_tag, MPC105_PICR1);
103 switch (reg1 & MPC105_PICR1_L2_MP) {
123 pcireg_t reg1, reg2; local
126 reg1 = pci_conf_read(pa->pa_pc, pa->pa_tag, MPC106_PICR1);
146 switch (reg1 & MPC106_PICR1_EXT_L2_EN) {
148 switch (reg1 & MPC106_PICR1_L2_MP) {
164 switch (reg1 & MPC106_PICR1_L2_MP) {
182 pcireg_t reg1; local
188 reg1 = pci_conf_read(pa->pa_pc, pa->pa_tag
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/clk/
nouveau_nvkm_subdev_clk_nv04.c 54 nv04_clk_pll_prog(struct nvkm_clk *clk, u32 reg1, struct nvkm_pll_vals *pv)
62 if (reg1 > 0x405c)
63 setPLL_double_highregs(devinit, reg1, pv);
65 setPLL_double_lowregs(devinit, reg1, pv);
67 setPLL_single(devinit, reg1, pv);
priv.h 28 int nv04_clk_pll_prog(struct nvkm_clk *, u32 reg1, struct nvkm_pll_vals *);
  /src/sys/arch/sgimips/ioc/
oioc.c 98 uint32_t reg1, reg2; local
118 reg1 = 12 << OIOC2_CONFIG_HIWAT_SHFT;
119 reg1 |= OIOC2_CONFIG_BURST_MASK;
120 bus_space_write_4(sc->sc_iot, sc->sc_ioh, OIOC2_CONFIG, reg1);
123 if ((reg2 & (reg1 | OIOC2_CONFIG_NOSYNC_MASK)) == reg1)
  /src/sys/arch/hppa/spmath/
md.h 75 #define mdrr(reg1,reg2,result) {result_hi = reg1;result_lo = reg2;}
  /src/external/gpl3/binutils/dist/gas/config/
tc-microblaze.c 888 unsigned reg1; local
933 op_end = parse_reg (op_end + 1, &reg1); /* Get rd. */
937 reg1 = 0;
955 if (check_spl_reg (& reg1))
965 inst |= (reg1 << RD_LOW) & RD_MASK;
971 inst |= (reg1 << RD_LOW) & RD_MASK;
980 op_end = parse_reg (op_end + 1, &reg1); /* Get rd. */
984 reg1 = 0;
999 if (check_spl_reg (& reg1))
1047 count = 32 - reg1;
    [all...]
  /src/external/gpl3/binutils.old/dist/gas/config/
tc-microblaze.c 885 unsigned reg1; local
930 op_end = parse_reg (op_end + 1, &reg1); /* Get rd. */
934 reg1 = 0;
952 if (check_spl_reg (& reg1))
962 inst |= (reg1 << RD_LOW) & RD_MASK;
968 inst |= (reg1 << RD_LOW) & RD_MASK;
977 op_end = parse_reg (op_end + 1, &reg1); /* Get rd. */
981 reg1 = 0;
996 if (check_spl_reg (& reg1))
1044 count = 32 - reg1;
    [all...]
  /src/external/gpl3/gdb/dist/sim/testsuite/bfin/
move.s 9 .macro move reg0:req, reg1:req, clobber:req
11 imm32 \reg1, 0x12345678
13 \reg0 = \reg1;
load.s 9 .macro load32 num:req, reg0:req, reg1:req
11 imm32 \reg1 \num
12 CC = \reg0 == \reg1
29 .macro load16z num:req reg0:req reg1:req
31 imm32 \reg1 \num
32 CC = \reg0 == \reg1
48 .macro load16x num:req reg0:req reg1:req
50 imm32 \reg1, \num
51 CC = \reg0 == \reg1
  /src/external/gpl3/gdb.old/dist/sim/testsuite/bfin/
move.s 9 .macro move reg0:req, reg1:req, clobber:req
11 imm32 \reg1, 0x12345678
13 \reg0 = \reg1;
load.s 9 .macro load32 num:req, reg0:req, reg1:req
11 imm32 \reg1 \num
12 CC = \reg0 == \reg1
29 .macro load16z num:req reg0:req reg1:req
31 imm32 \reg1 \num
32 CC = \reg0 == \reg1
48 .macro load16x num:req reg0:req reg1:req
50 imm32 \reg1, \num
51 CC = \reg0 == \reg1
  /src/crypto/external/apache2/openssl/dist/crypto/perlasm/
x86nasm.pl 43 { my($size,$addr,$reg1,$reg2,$idx)=@_;
46 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
69 $ret .= "+$reg1" if ($reg1 ne "");
72 { $ret .= "$reg1"; }
x86gas.pl 77 { my($addr,$reg1,$reg2,$idx)=@_;
80 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
86 $reg1 = "%$reg1" if ($reg1);
93 $ret .= "($reg1,$reg2,$idx)";
95 elsif ($reg1)
96 { $ret .= "($reg1)"; }
  /src/crypto/external/bsd/openssl/dist/crypto/perlasm/
x86nasm.pl 43 { my($size,$addr,$reg1,$reg2,$idx)=@_;
46 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
69 $ret .= "+$reg1" if ($reg1 ne "");
72 { $ret .= "$reg1"; }
x86gas.pl 77 { my($addr,$reg1,$reg2,$idx)=@_;
80 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
86 $reg1 = "%$reg1" if ($reg1);
93 $ret .= "($reg1,$reg2,$idx)";
95 elsif ($reg1)
96 { $ret .= "($reg1)"; }
  /src/crypto/external/bsd/openssl.old/dist/crypto/perlasm/
x86nasm.pl 43 { my($size,$addr,$reg1,$reg2,$idx)=@_;
46 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
69 $ret .= "+$reg1" if ($reg1 ne "");
72 { $ret .= "$reg1"; }
x86gas.pl 77 { my($addr,$reg1,$reg2,$idx)=@_;
80 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
86 $reg1 = "%$reg1" if ($reg1);
93 $ret .= "($reg1,$reg2,$idx)";
95 elsif ($reg1)
96 { $ret .= "($reg1)"; }
  /src/sys/dev/ic/
rtwvar.h 118 * Complete outstanding read and/or write ops on [reg0, reg1]
119 * ([reg1, reg0]) before starting new ops on the same region. See
123 rtw_barrier(const struct rtw_regs *r, int reg0, int reg1, int flags)
125 bus_space_barrier(r->r_bt, r->r_bh, MIN(reg0, reg1),
126 MAX(reg0, reg1) - MIN(reg0, reg1) + 4, flags);
133 #define RTW_SYNC(regs, reg0, reg1) \
134 rtw_barrier(regs, reg0, reg1, BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE)
137 #define RTW_WBW(regs, reg0, reg1) \
138 rtw_barrier(regs, reg0, reg1, BUS_SPACE_BARRIER_WRITE
    [all...]
  /src/external/gpl3/gcc/dist/gcc/
auto-inc-dec.cc 143 the forms are reg1 + reg2. */
279 for the reg1-reg2 case. Note that we do not have a INC_POS_REG
308 /* Parsed fields of an inc insn of the form "reg_res = reg0+reg1" or
315 bool reg1_is_const; /* True if reg1 is const, false if reg1 is a reg. */
319 rtx reg1; member in struct:inc_insn
320 enum inc_state reg1_state;/* The form of the const if reg1 is a const. */
321 HOST_WIDE_INT reg1_val;/* Value if reg1 is const. */
348 REGNO (inc_insn.reg0), REGNO (inc_insn.reg1));
360 REGNO (inc_insn.reg_res), REGNO (inc_insn.reg1));
379 rtx reg1; \/* This is either a reg or a const depending on member in struct:mem_insn
1363 rtx reg1 = XEXP (XEXP (x, 0), 1); local
    [all...]
  /src/external/gpl3/gcc.old/dist/gcc/
auto-inc-dec.cc 143 the forms are reg1 + reg2. */
279 for the reg1-reg2 case. Note that we do not have a INC_POS_REG
308 /* Parsed fields of an inc insn of the form "reg_res = reg0+reg1" or
315 bool reg1_is_const; /* True if reg1 is const, false if reg1 is a reg. */
319 rtx reg1; member in struct:inc_insn
320 enum inc_state reg1_state;/* The form of the const if reg1 is a const. */
321 HOST_WIDE_INT reg1_val;/* Value if reg1 is const. */
348 REGNO (inc_insn.reg0), REGNO (inc_insn.reg1));
360 REGNO (inc_insn.reg_res), REGNO (inc_insn.reg1));
379 rtx reg1; \/* This is either a reg or a const depending on member in struct:mem_insn
1363 rtx reg1 = XEXP (XEXP (x, 0), 1); local
    [all...]
  /src/sys/arch/hpcsh/dev/
psh3lcd.c 72 uint8_t reg1; member in struct:psh3lcd_x0_bcd
83 uint8_t reg1; member in struct:psh3lcd_xx0_bcd
144 bcr1 == psh3lcd_x0_bcd[i].reg1 &&
161 for (i = 0; psh3lcd_xx0_bcd[i].reg1 != 0; i++)
162 if (bcr1 == psh3lcd_xx0_bcd[i].reg1 &&
165 if (psh3lcd_xx0_bcd[i].reg1 == 0)
174 _reg_write_1(PSH3LCD_BRIGHTNESS_REG1, psh3lcd_xx0_bcd[index].reg1);
183 _reg_write_1(PSH3LCD_BRIGHTNESS_REG1, psh3lcd_x0_bcd[index].reg1);

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