HomeSort by: relevance | last modified time | path
    Searched refs:reg2 (Results 1 - 25 of 31) sorted by relevancy

1 2

  /src/sys/arch/hppa/spmath/
md.h 75 #define mdrr(reg1,reg2,result) {result_hi = reg1;result_lo = reg2;}
  /src/sys/arch/powerpc/pci/
pchb.c 80 pcireg_t reg1, reg2; local in function:mpc105_print
84 reg2 = pci_conf_read(pa->pa_pc, pa->pa_tag, MPC105_PICR2);
87 switch (reg2 & MPC105_PICR2_L2_SIZE) {
123 pcireg_t reg1, reg2; local in function:mpc106_print
127 reg2 = pci_conf_read(pa->pa_pc, pa->pa_tag, MPC106_PICR2);
130 switch (reg2 & MPC106_PICR2_L2_SIZE) {
184 pcireg_t reg2; local in function:ibm82660_print
191 reg2 = in32rb(PREP_BUS_SPACE_IO+IBM_82660_SYSTEM_CTRL);
192 if (reg2 & IBM_82660_SYSTEM_CTRL_L2_EN) {
197 if (reg2 & IBM_82660_SYSTEM_CTRL_L2_MI
    [all...]
  /src/sys/dev/acpi/
ipmi_acpi.c 88 bus_addr_t reg2; local in function:ipmi_acpi_attach
145 reg2 = 0;
149 reg2 = (bus_addr_t)io->ar_base;
153 reg2 = mem->ar_base;
156 if (reg2 > ia->iaa_if_iobase)
157 ia->iaa_if_iospacing = reg2 - ia->iaa_if_iobase;
  /src/sys/arch/sgimips/ioc/
oioc.c 98 uint32_t reg1, reg2; local in function:oioc_attach
122 reg2 = bus_space_read_4(sc->sc_iot, sc->sc_ioh, OIOC2_CONFIG);
123 if ((reg2 & (reg1 | OIOC2_CONFIG_NOSYNC_MASK)) == reg1)
135 (u_quad_t)reg2 & 0xffffffff);
  /src/sys/arch/hppa/hppa/
locore.S 89 #define _DEBUG_PUTCHAR(reg1, reg2) ! \
91 stb %reg2, R%COM1_TX_REG(%sr1, %reg1) ! \
93 ldi 1, %reg2 ! \
95 sub %reg1, %reg2, %reg1
96 #define DEBUG_PUTCHAR(reg1, reg2, ch) ! \
97 ldi ch, %reg2 ! \
98 _DEBUG_PUTCHAR(reg1,reg2)
99 #define _DEBUG_DUMPN(reg1, reg2, reg3, p) ! \
100 extru %reg3, p, 4, %reg2 ! \
101 comib,>>,n 10, %reg2, 0 !
    [all...]
  /src/sys/arch/hpcsh/dev/
psh3lcd.c 73 uint8_t reg2; member in struct:psh3lcd_x0_bcd
84 uint8_t reg2; member in struct:psh3lcd_xx0_bcd
145 bcr2 == psh3lcd_x0_bcd[i].reg2)
163 bcr2 == psh3lcd_xx0_bcd[i].reg2)
175 _reg_write_1(PSH3LCD_BRIGHTNESS_REG2, psh3lcd_xx0_bcd[index].reg2);
184 _reg_write_1(PSH3LCD_BRIGHTNESS_REG2, psh3lcd_x0_bcd[index].reg2);
  /src/games/warp/
config.sh 104 reg2='register'
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dce120/
amdgpu_irq_service_dce120.c 110 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
118 .ack_reg = SRI(reg2, block, reg_num),\
120 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
122 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dcn10/
amdgpu_irq_service_dcn10.c 191 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
199 .ack_reg = SRI(reg2, block, reg_num),\
201 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
203 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dcn20/
amdgpu_irq_service_dcn20.c 193 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
201 .ack_reg = SRI(reg2, block, reg_num),\
203 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
205 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dcn21/
amdgpu_irq_service_dcn21.c 189 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
197 .ack_reg = SRI(reg2, block, reg_num),\
199 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
201 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/
amdgpu_hw_ddc.c 115 uint32_t reg2 __unused;
119 reg2 = REG_GET_2(gpio.MASK_reg,
  /src/sys/arch/hpcmips/dev/
plumicu.c 332 plumreg_t reg1, reg2, reg_ext, reg_pccard; local in function:plumicu_intr
362 reg2 = pic->ic_ackreg2 == PLUM_INT_PCCINTS_REG
365 if (pic->ic_ackpat2 & reg2)
it8368.c 354 u_int16_t reg2; local in function:it8368_intr
355 reg2 = reg & ~(IT8368_PIN_BCRDRDY|IT8368_PIN_CRDDET2);
357 dbg_bit_print(reg2);
  /src/sys/dev/isa/
ess.c 616 u_char reg2; local in function:ess_identify
637 reg2 = ess_rdsp(sc);
638 if (((reg2 & 0xf0) != 0x80) ||
639 ((reg2 & 0x0f) < 8)) {
647 sc->sc_version = (reg1 << 8) + reg2;
655 reg2 = reg1 ^ 0x04; /* toggle bit 2 */
657 ess_write_mix_reg(sc, ESS_MREG_VOLUME_CTRL, reg2);
659 if (ess_read_mix_reg(sc, ESS_MREG_VOLUME_CTRL) != reg2) {
684 reg2 = reg1 ^ 0xff; /* toggle all bits */
686 ess_write_mix_reg(sc, ESS_MREG_SAMPLE_RATE, reg2);
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/devinit/
nouveau_nvkm_subdev_devinit_nv04.c 209 uint32_t reg2 = reg1 + ((reg1 == 0x680520) ? 0x5c : 0x70); local in function:setPLL_double_highregs
211 uint32_t oldpll2 = !nv3035 ? nvkm_rd32(device, reg2) : 0;
271 nvkm_wr32(device, reg2, pll2);
  /src/sys/lib/libunwind/
DwarfParser.hpp 318 uint64_t reg2; local in function:_Unwind::CFI_Parser::parseInstructions
376 reg2 = R::dwarf2regno(addressSpace.getULEB128(p, instructionsEnd));
379 if (reg2 > kMaxRegisterNumber)
382 results->savedRegisters[reg].value = reg2;
  /src/sys/dev/usb/
uchcom.c 447 uint8_t reg1, uint8_t val1, uint8_t reg2, uint8_t val2)
452 (unsigned)reg2, (unsigned)val2));
455 reg1|((uint16_t)reg2<<8), val1|((uint16_t)val2<<8));
460 uint8_t reg1, uint8_t *rval1, uint8_t reg2, uint8_t *rval2)
468 reg1|((uint16_t)reg2<<8), 0, buf, sizeof(buf), &actin);
475 (unsigned)reg2, (unsigned)buf[1]));
  /src/sys/dev/sbus/
dbri.c 783 uint32_t reg2; local in function:mmcodec_init
786 reg2 = bus_space_read_4(iot, ioh, DBRI_REG2);
787 DPRINTF("mmcodec_init: PIO reads %x\n", reg2);
789 if (reg2 & DBRI_PIO2) {
794 if (reg2 & DBRI_PIO0) {
800 if ((reg2 & DBRI_PIO2) && (reg2 & DBRI_PIO0)) {
806 if (!(reg2 & (DBRI_PIO0|DBRI_PIO2))) {
  /src/sys/dev/ic/
tcic2.c 836 int reg2; local in function:tcic_chip_do_mem_map
837 reg2 = tcic_read_ind_2(h, TCIC_WR_MCTL_N(7-hwwin));
838 reg2 &= ~TCIC_MCTL_WSCNT_MASK;
839 reg2 |= wscnt & TCIC_MCTL_WSCNT_MASK;
840 tcic_write_ind_2(h, TCIC_WR_MCTL_N(7-hwwin), reg2);
aic6915.c 1232 uint32_t reg0, reg1, reg2; local in function:sf_set_filter_perfect
1236 reg2 = enaddr[1] | (enaddr[0] << 8);
1240 sf_genreg_write(sc, SF_PERFECT_BASE + (slot * 0x10) + 8, reg2);
  /src/sys/dev/ieee1394/
fwohci.c 1144 uint32_t reg, reg2; local in function:fwohci_probe_phy
1172 reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG);
1175 sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5;
1187 reg2 = fwphy_rddata(sc, 5);
1196 reg2 |= 0x03;
1204 reg2 &= ~0x83;
1207 reg2 = fwphy_wrdata(sc, 5, reg2);
1224 uint32_t reg, reg2; local in function:fwohci_reset
1260 reg2 = reg | OHCI_BUSFNC
    [all...]
  /src/sys/external/bsd/drm/dist/shared-core/
mga_drv.h 344 #define DMA_BLOCK( reg0, val0, reg1, val1, reg2, val2, reg3, val3 ) \
348 (DMAREG( reg2 ) << 16) | \
  /src/sys/external/bsd/drm2/dist/drm/mga/
mga_drv.h 342 #define DMA_BLOCK(reg0, val0, reg1, val1, reg2, val2, reg3, val3) \
346 (DMAREG(reg2) << 16) | \
  /src/sys/dev/pcmcia/
pcmcia_cis.c 1049 u_int reg, reg2; local in function:decode_cftable_entry
1170 reg2 = pcmcia_tuple_read_1(tuple, idx);
1178 } while (reg2 & 0x80);

Completed in 90 milliseconds

1 2