| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| clearstate_defs.h | 37 const unsigned int reg_index; member in struct:cs_extent_def
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| amdgpu_psp.h | 357 extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
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| amdgpu_psp.c | 128 int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
136 val = RREG32(reg_index);
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| amdgpu_gfx_v6_0.c | 2071 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2905 buffer[count++] = cpu_to_le32(ext->reg_index - 0xa000);
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| amdgpu_gfx_v10_0.c | 974 buffer[count++] = cpu_to_le32(ext->reg_index -
2692 amdgpu_ring_write(ring, ext->reg_index -
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| amdgpu_gfx_v7_0.c | 2570 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
4000 buffer[count++] = cpu_to_le32(ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
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| amdgpu_gfx_v8_0.c | 1274 buffer[count++] = cpu_to_le32(ext->reg_index -
4204 ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
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| amdgpu_gfx_v9_0.c | 1652 buffer[count++] = cpu_to_le32(ext->reg_index -
3147 ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
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| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| clearstate_defs.h | 37 const unsigned int reg_index; member in struct:cs_extent_def
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| radeon_sumo_dpm.c | 481 u32 reg_index = index / 4; local in function:sumo_set_divider_value
485 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
488 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
491 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
494 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
587 u32 reg_index = index / 4; local in function:sumo_power_level_enable
591 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
594 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
597 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
600 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4)
[all...] |
| radeon_evergreen.c | 4309 data = (cs_data[i].section[j].reg_index * 4) & 0xffffffff;
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| radeon_si.c | 5745 buffer[count++] = cpu_to_le32(ext->reg_index - 0xa000);
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| radeon_cik.c | 6750 buffer[count++] = cpu_to_le32(ext->reg_index - 0xa000);
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| /src/usr.bin/scmdctl/ |
| common.c | 193 int reg_index; local in function:common_set_motor
203 reg_index = a_module * 2;
205 reg_index++;
206 reg = SCMD_REG_MA_DRIVE + reg_index;
209 fprintf(stderr,"common_set_motor: reg_index: %d ; reg: %02X ; reg_v: %d\n",reg_index,reg,reg_v);
221 uint8_t reg, reg_index = 0, reg_offset = 0; local in function:common_invert_motor
243 reg_index = 1 << motor_index;
246 fprintf(stderr,"common_invert_motor: remote invert: motor_index: %d ; reg_offset: %d ; reg_index: %02X ; reg: %02X\n",motor_index,reg_offset,reg_index,reg)
263 uint8_t reg, reg_index = 0, reg_offset = 0; local in function:common_bridge_motor
[all...] |
| /src/usr.sbin/gspa/gspa/ |
| gsp_gram.y | 108 { $$ = reg_index($2, $4); }
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| gsp_ass.h | 153 operand reg_index(int, expr);
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| gsp_act.c | 146 reg_index(int reg, expr disp) function in typeref:typename:operand
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| amdgpu_dce_audio.c | 63 uint32_t reg_index,
70 AZALIA_ENDPOINT_REG_INDEX, reg_index);
77 reg_index, reg_data);
80 static uint32_t read_indirect_azalia_reg(struct audio *audio, uint32_t reg_index)
88 AZALIA_ENDPOINT_REG_INDEX, reg_index);
94 reg_index, value);
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