| /src/sys/external/bsd/drm2/dist/drm/amd/display/dmub/src/ |
| dmub_reg.h | 39 #define REG_OFFSET(reg_name) (BASE(mm##reg_name##_BASE_IDX) + mm##reg_name)
41 #define FD_SHIFT(reg_name, field) reg_name##__##field##__SHIFT
43 #define FD_MASK(reg_name, field) reg_name##__##field##_MASK
49 #define FN(reg_name, field) FD(reg_name##__##field)
60 #define REG_SET_N(reg_name, n, initial_val, ...)
[all...] |
| /src/sys/arch/mips/mips/ |
| db_disasm.c | 174 static const char * const reg_name[32] = { variable in typeref:typename:const char * const[32]
181 static const char * const reg_name[32] = { variable in typeref:typename:const char * const[32]
300 reg_name[i.RType.rd],
301 reg_name[i.RType.rs]);
325 reg_name[i.RType.rd],
326 reg_name[i.RType.rt],
337 reg_name[i.RType.rd],
338 reg_name[i.RType.rt],
339 reg_name[i.RType.rs]);
344 db_printf("\t%s", reg_name[i.RType.rd])
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dcn20/ |
| amdgpu_hw_factory_dcn20.c | 64 #define REG(reg_name)\
65 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
67 #define SF_HPD(reg_name, field_name, post_fix)\
68 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
70 #define REGI(reg_name, block, id)\
71 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
72 mm ## block ## id ## _ ## reg_name
74 #define SF(reg_name, field_name, post_fix)\
75 .field_name = reg_name ## __ ## field_name ## post_fi
[all...] |
| amdgpu_hw_translate_dcn20.c | 60 #define REG(reg_name)\
61 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
62 #define SF_HPD(reg_name, field_name, post_fix)\
63 .field_name = reg_name ## __ ## field_name ## post_fix
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dcn21/ |
| amdgpu_hw_factory_dcn21.c | 62 #define REG(reg_name)\
63 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
65 #define SF_HPD(reg_name, field_name, post_fix)\
66 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
68 #define REGI(reg_name, block, id)\
69 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
70 mm ## block ## id ## _ ## reg_name
72 #define SF(reg_name, field_name, post_fix)\
73 .field_name = reg_name ## __ ## field_name ## post_fi
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn10/ |
| rv1_clk_mgr_clk.c | 48 #define CLK_REG(reg_name, block, inst)\
49 CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
50 mm ## block ## _ ## inst ## _ ## reg_name
52 #define REG(reg_name) \
53 CLK_REG(reg_name, CLK0, 0)
|
| amdgpu_rv1_clk_mgr_vbios_smu.c | 67 #define REG(reg_name) \
68 (MP1_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
70 #define FN(reg_name, field) \
71 FD(reg_name##__##field)
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dce120/ |
| amdgpu_hw_factory_dce120.c | 51 #define SF_HPD(reg_name, field_name, post_fix)\
52 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
55 #define SF_HPD(reg_name, field_name, post_fix)\
56 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
65 #define REG(reg_name)\
66 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
68 #define REGI(reg_name, block, id)\
69 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
70 mm ## block ## id ## _ ## reg_name
[all...] |
| amdgpu_hw_translate_dce120.c | 56 #define REG(reg_name)\
57 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
59 #define REGI(reg_name, block, id)\
60 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
61 mm ## block ## id ## _ ## reg_name
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dcn10/ |
| amdgpu_hw_factory_dcn10.c | 52 #define SF_HPD(reg_name, field_name, post_fix)\
53 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
62 #define REG(reg_name)\
63 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
65 #define REGI(reg_name, block, id)\
66 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
67 mm ## block ## id ## _ ## reg_name
97 #define SF_DDC(reg_name, field_name, post_fix)\
98 .field_name = reg_name ## __ ## field_name ## post_fi
[all...] |
| amdgpu_hw_translate_dcn10.c | 56 #define REG(reg_name)\
57 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
59 #define REGI(reg_name, block, id)\
60 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
61 mm ## block ## id ## _ ## reg_name
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| dcn20_vmid.h | 39 #define SRI(reg_name, block, id)\
40 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
41 mm ## block ## id ## _ ## reg_name
43 #define SF(reg_name, field_name, post_fix)\
44 .field_name = reg_name ## __ ## field_name ## post_fix
|
| dcn20_dccg.h | 46 #define DCCG_SF(reg_name, field_name, post_fix)\
47 .field_name = reg_name ## __ ## field_name ## post_fix
49 #define DCCG_SFI(reg_name, field_name, field_prefix, inst, post_fix)\
50 .field_prefix ## _ ## field_name[inst] = reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix
|
| dcn20_dwb.h | 39 #define SR(reg_name)\
40 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
41 mm ## reg_name
43 #define SRI(reg_name, block, id)\
44 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
45 mm ## block ## id ## _ ## reg_name
47 #define SRI2(reg_name, block, id)\
48 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) +
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/ |
| dm_services.h | 116 #define get_reg_field_value(reg_value, reg_name, reg_field)\
119 reg_name ## __ ## reg_field ## _MASK,\
120 reg_name ## __ ## reg_field ## __SHIFT)
132 #define set_reg_field_value(reg_value, value, reg_name, reg_field)\
136 reg_name ## __ ## reg_field ## _MASK,\
137 reg_name ## __ ## reg_field ## __SHIFT)
177 #define generic_reg_update_soc15(ctx, inst_offset, reg_name, n, ...)\
178 generic_reg_update_ex(ctx, DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX] + mm##reg_name + inst_offset, \
181 #define generic_reg_set_soc15(ctx, inst_offset, reg_name, n, ...)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dce110/ |
| amdgpu_hw_factory_dce110.c | 47 #define SF_HPD(reg_name, field_name, post_fix)\
48 .field_name = reg_name ## __ ## field_name ## post_fix
50 #define REG(reg_name)\
51 mm ## reg_name
53 #define REGI(reg_name, block, id)\
54 mm ## block ## id ## _ ## reg_name
88 #define SF_DDC(reg_name, field_name, post_fix)\
89 .field_name = reg_name ## __ ## field_name ## post_fix
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/ |
| reg_helper.h | 41 #define REG_READ(reg_name) \
42 dm_read_reg(CTX, REG(reg_name))
44 #define REG_WRITE(reg_name, value) \
45 dm_write_reg(CTX, REG(reg_name), value)
56 #define REG_SET_N(reg_name, n, initial_val, ...) \
58 REG(reg_name), \
62 #define FN(reg_name, field) \
63 FD(reg_name##__##field)
65 #define REG_SET(reg_name, initial_val, field, val) \
66 REG_SET_N(reg_name, 1, initial_val,
[all...] |
| /src/sys/arch/arc/arc/ |
| minidebug.c | 109 static char *reg_name[32] = { variable in typeref:typename:char * [32]
686 reg_name[i.RType.rd],
687 reg_name[i.RType.rs]);
702 reg_name[i.RType.rd],
703 reg_name[i.RType.rt],
714 reg_name[i.RType.rd],
715 reg_name[i.RType.rt],
716 reg_name[i.RType.rs]);
721 printf("\t%s", reg_name[i.RType.rd]);
730 printf("\t%s", reg_name[i.RType.rs])
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn21/ |
| amdgpu_rn_clk_mgr_vbios_smu.c | 40 #define REG(reg_name) \
41 (MP0_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
43 #define FN(reg_name, field) \
44 FD(reg_name##__##field)
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| dcn10_dwb.h | 38 #define SR(reg_name)\
39 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
40 mm ## reg_name
42 #define SRI(reg_name, block, id)\
43 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
44 mm ## block ## id ## _ ## reg_name
47 #define SRII(reg_name, block, id)\
48 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) +
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/ |
| clk_mgr_internal.h | 85 #define CLK_SRI(reg_name, block, inst)\
86 .reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
87 mm ## block ## _ ## inst ## _ ## reg_name
106 #define CLK_SF(reg_name, field_name, post_fix)\
107 .field_name = reg_name ## __ ## field_name ## post_fix
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dce80/ |
| amdgpu_hw_factory_dce80.c | 46 #define REG(reg_name)\
47 mm ## reg_name
88 #define SF_DDC(reg_name, field_name, post_fix)\
89 .field_name = reg_name ## __ ## field_name ## post_fix
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/bios/ |
| amdgpu_bios_parser_helper.c | 59 #define FN(reg_name, field_name) \
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce110/ |
| amdgpu_dce110_clk_mgr.c | 40 #define SR(reg_name)\
41 .reg_name = mm ## reg_name
44 #define SRI(reg_name, block, id)\
45 .reg_name = mm ## block ## id ## _ ## reg_name
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce112/ |
| amdgpu_dce112_clk_mgr.c | 42 #define SR(reg_name)\
43 .reg_name = mm ## reg_name
46 #define SRI(reg_name, block, id)\
47 .reg_name = mm ## block ## id ## _ ## reg_name
|
