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  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dce120/
amdgpu_irq_service_dce120.c 110 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
111 .enable_reg = SRI(reg1, block, reg_num),\
113 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
115 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
116 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
118 .ack_reg = SRI(reg2, block, reg_num),\
120 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
122 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
124 #define hpd_int_entry(reg_num)\
125 [DC_IRQ_SOURCE_HPD1 + reg_num] = {
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dcn10/
amdgpu_irq_service_dcn10.c 191 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
192 .enable_reg = SRI(reg1, block, reg_num),\
194 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
196 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
197 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
199 .ack_reg = SRI(reg2, block, reg_num),\
201 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
203 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
205 #define hpd_int_entry(reg_num)\
206 [DC_IRQ_SOURCE_HPD1 + reg_num] = {
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dcn20/
amdgpu_irq_service_dcn20.c 193 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
194 .enable_reg = SRI(reg1, block, reg_num),\
196 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
198 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
199 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
201 .ack_reg = SRI(reg2, block, reg_num),\
203 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
205 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
209 #define hpd_int_entry(reg_num)\
210 [DC_IRQ_SOURCE_HPD1 + reg_num] = {
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dcn21/
amdgpu_irq_service_dcn21.c 189 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
190 .enable_reg = SRI(reg1, block, reg_num),\
192 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
194 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
195 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
197 .ack_reg = SRI(reg2, block, reg_num),\
199 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
201 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
205 #define hpd_int_entry(reg_num)\
206 [DC_IRQ_SOURCE_HPD1 + reg_num] = {
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dce110/
amdgpu_irq_service_dce110.c 96 #define hpd_int_entry(reg_num)\
97 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
98 .enable_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
104 .ack_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
107 .status_reg = mmHPD ## reg_num ## _DC_HPD_INT_STATUS,\
111 #define hpd_rx_int_entry(reg_num)\
112 [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
113 .enable_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
118 .ack_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
121 .status_reg = mmHPD ## reg_num ## _DC_HPD_INT_STATUS,
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dce80/
amdgpu_irq_service_dce80.c 99 #define hpd_int_entry(reg_num)\
100 [DC_IRQ_SOURCE_INVALID + reg_num] = {\
101 .enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
107 .ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
110 .status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\
114 #define hpd_rx_int_entry(reg_num)\
115 [DC_IRQ_SOURCE_HPD6 + reg_num] = {\
116 .enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
121 .ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
124 .status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,
    [all...]
  /src/sys/dev/pci/
unichromehw.h 255 int reg_num; member in struct:iga1_hor_total
261 int reg_num; member in struct:iga1_hor_addr
267 int reg_num; member in struct:iga1_hor_blank_start
273 int reg_num; member in struct:iga1_hor_blank_end
279 int reg_num; member in struct:iga1_hor_sync_start
285 int reg_num; member in struct:iga1_hor_sync_end
291 int reg_num; member in struct:iga1_ver_total
297 int reg_num; member in struct:iga1_ver_addr
303 int reg_num; member in struct:iga1_ver_blank_start
309 int reg_num; member in struct:iga1_ver_blank_end
315 int reg_num; member in struct:iga1_ver_sync_start
321 int reg_num; member in struct:iga1_ver_sync_end
332 int reg_num; member in struct:iga2_shadow_hor_total
338 int reg_num; member in struct:iga2_shadow_hor_blank_end
345 int reg_num; member in struct:iga2_shadow_ver_total
351 int reg_num; member in struct:iga2_shadow_ver_addr
357 int reg_num; member in struct:iga2_shadow_ver_blank_start
363 int reg_num; member in struct:iga2_shadow_ver_blank_end
369 int reg_num; member in struct:iga2_shadow_ver_sync_start
375 int reg_num; member in struct:iga2_shadow_ver_sync_end
385 int reg_num; member in struct:iga2_hor_total
391 int reg_num; member in struct:iga2_hor_addr
397 int reg_num; member in struct:iga2_hor_blank_start
403 int reg_num; member in struct:iga2_hor_blank_end
409 int reg_num; member in struct:iga2_hor_sync_start
415 int reg_num; member in struct:iga2_hor_sync_end
421 int reg_num; member in struct:iga2_ver_total
427 int reg_num; member in struct:iga2_ver_addr
433 int reg_num; member in struct:iga2_ver_blank_start
439 int reg_num; member in struct:iga2_ver_blank_end
445 int reg_num; member in struct:iga2_ver_sync_start
451 int reg_num; member in struct:iga2_ver_sync_end
457 int reg_num; member in struct:iga1_offset
463 int reg_num; member in struct:iga2_offset
474 int reg_num; member in struct:iga1_fetch_count
480 int reg_num; member in struct:iga2_fetch_count
491 int reg_num; member in struct:iga1_starting_addr
496 int reg_num; member in struct:iga2_starting_addr
507 int reg_num; member in struct:lcd_pwd_seq_td0
512 int reg_num; member in struct:lcd_pwd_seq_td1
517 int reg_num; member in struct:lcd_pwd_seq_td2
522 int reg_num; member in struct:lcd_pwd_seq_td3
535 int reg_num; member in struct:_lcd_hor_scaling_factor
540 int reg_num; member in struct:_lcd_ver_scaling_factor
573 int reg_num; member in struct:iga1_fifo_depth_select
578 int reg_num; member in struct:iga1_fifo_threshold_select
583 int reg_num; member in struct:iga1_fifo_high_threshold_select
588 int reg_num; member in struct:iga1_display_queue_expire_num
593 int reg_num; member in struct:iga2_fifo_depth_select
598 int reg_num; member in struct:iga2_fifo_threshold_select
603 int reg_num; member in struct:iga2_fifo_high_threshold_select
608 int reg_num; member in struct:iga2_display_queue_expire_num
    [all...]
unichromefb.c 825 regnum = iga1_crtc_reg.hor_total.reg_num;
831 regnum = iga1_crtc_reg.hor_addr.reg_num;
837 regnum = iga1_crtc_reg.hor_blank_start.reg_num;
844 regnum = iga1_crtc_reg.hor_blank_end.reg_num;
850 regnum = iga1_crtc_reg.hor_sync_start.reg_num;
857 regnum = iga1_crtc_reg.hor_sync_end.reg_num;
863 regnum = iga1_crtc_reg.ver_total.reg_num;
869 regnum = iga1_crtc_reg.ver_addr.reg_num;
875 regnum = iga1_crtc_reg.ver_blank_start.reg_num;
882 regnum = iga1_crtc_reg.ver_blank_end.reg_num;
    [all...]
  /src/external/gpl3/binutils/dist/gas/config/
tc-i386-intel.c 304 int reg_num; local
313 reg_num = e->X_add_number;
315 reg_num = e->X_md - 1;
317 if (reg_num < 0 || reg_num >= (int) i386_regtab_size)
323 if (!check_register (&i386_regtab[reg_num]))
326 register_prefix, i386_regtab[reg_num].reg_name);
337 if ((i386_regtab[reg_num].reg_type.bitfield.class == SReg
338 && i386_regtab[reg_num].reg_num == RegFlat
    [all...]
  /src/external/gpl3/binutils.old/dist/gas/config/
tc-i386-intel.c 304 int reg_num; local
313 reg_num = e->X_add_number;
315 reg_num = e->X_md - 1;
317 if (reg_num < 0 || reg_num >= (int) i386_regtab_size)
323 if (!check_register (&i386_regtab[reg_num]))
326 register_prefix, i386_regtab[reg_num].reg_name);
337 if ((i386_regtab[reg_num].reg_type.bitfield.class == SReg
338 && i386_regtab[reg_num].reg_num == RegFlat
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/
dm_services.h 185 #define get_reg_field_value_soc15(reg_value, block, reg_num, reg_name, reg_field)\
188 block ## reg_num ## _ ## reg_name ## __ ## reg_field ## _MASK,\
189 block ## reg_num ## _ ## reg_name ## __ ## reg_field ## __SHIFT)
191 #define set_reg_field_value_soc15(reg_value, value, block, reg_num, reg_name, reg_field)\
195 block ## reg_num ## _ ## reg_name ## __ ## reg_field ## _MASK,\
196 block ## reg_num ## _ ## reg_name ## __ ## reg_field ## __SHIFT)
  /src/external/gpl3/binutils/dist/libsframe/
sframe-dump.c 28 unsigned int reg_num; member in struct:__anon10863
58 sframe_get_reg_name (uint8_t abi_arch, unsigned int reg_num, char *buf,
81 if (abi_reg_map->reg_map[0].reg_num == reg_num)
83 else if (abi_reg_map->reg_map[1].reg_num == reg_num)
89 snprintf (buf, buf_size, "r%u", reg_num);
320 unsigned int reg_num, bool reg_p, int32_t offset,
329 reg_name = sframe_get_reg_name (abi_arch, reg_num, temp_reg_name,
  /src/external/gpl3/gdb.old/dist/gdb/python/
py-registers.c 370 int *reg_num)
381 *reg_num = user_reg_map_name_to_regnum (gdbarch, reg_name.get (),
383 if (*reg_num >= 0)
399 *reg_num = (int) value;
413 *reg_num = reg->regnum;
  /src/external/gpl3/gdb/dist/gdb/python/
py-registers.c 370 int *reg_num)
381 *reg_num = user_reg_map_name_to_regnum (gdbarch, reg_name.get (),
383 if (*reg_num >= 0)
399 *reg_num = (int) value;
412 *reg_num = reg->regnum;
  /src/external/gpl3/gdb.old/dist/sim/aarch64/
cpustate.c 38 #define reg_num(reg) (((reg) == R31 && !r31_is_sp) ? 32 : (reg)) macro
81 return AARCH64_SIM_CPU (cpu)->gr[reg_num(reg)].u64;
87 return AARCH64_SIM_CPU (cpu)->gr[reg_num(reg)].s64;
93 return AARCH64_SIM_CPU (cpu)->gr[reg_num(reg)].u32;
99 return AARCH64_SIM_CPU (cpu)->gr[reg_num(reg)].s32;
149 return AARCH64_SIM_CPU (cpu)->gr[reg_num(reg)].u16;
155 return AARCH64_SIM_CPU (cpu)->gr[reg_num(reg)].s16;
161 return AARCH64_SIM_CPU (cpu)->gr[reg_num(reg)].u8;
167 return AARCH64_SIM_CPU (cpu)->gr[reg_num(reg)].s8;
  /src/external/gpl3/gdb/dist/sim/aarch64/
cpustate.c 38 #define reg_num(reg) (((reg) == R31 && !r31_is_sp) ? 32 : (reg)) macro
81 return AARCH64_SIM_CPU (cpu)->gr[reg_num(reg)].u64;
87 return AARCH64_SIM_CPU (cpu)->gr[reg_num(reg)].s64;
93 return AARCH64_SIM_CPU (cpu)->gr[reg_num(reg)].u32;
99 return AARCH64_SIM_CPU (cpu)->gr[reg_num(reg)].s32;
149 return AARCH64_SIM_CPU (cpu)->gr[reg_num(reg)].u16;
155 return AARCH64_SIM_CPU (cpu)->gr[reg_num(reg)].s16;
161 return AARCH64_SIM_CPU (cpu)->gr[reg_num(reg)].u8;
167 return AARCH64_SIM_CPU (cpu)->gr[reg_num(reg)].s8;
  /src/external/gpl3/binutils/dist/gprofng/common/
hwcentry.h 109 regno_t reg_num; /* register in CPU, aka picnum, or REGNO_ANY */ member in struct:__anon10196
166 * <list[]->reg_num>:
261 * <pret_ctr->reg_num>:
301 * <ctr->reg_num>:
316 * Array of legal <reg_num> values. Terminated by REGNO_ANY.
hwcfuncs.c 164 " reg_num=%d, timecvt=%d, memop=%d, "
166 hdr, phwcdef->name, phwcdef->int_name, phwcdef->reg_num,
238 hwcdef[idx].reg_num = REGNO_ANY;
323 /* reg_num */
336 hwcdef[idx].reg_num = reg;
  /src/external/gpl3/binutils.old/dist/gprofng/common/
hwcentry.h 109 regno_t reg_num; /* register in CPU, aka picnum, or REGNO_ANY */ member in struct:__anon11669
166 * <list[]->reg_num>:
261 * <pret_ctr->reg_num>:
301 * <ctr->reg_num>:
316 * Array of legal <reg_num> values. Terminated by REGNO_ANY.
hwcfuncs.c 164 " reg_num=%d, timecvt=%d, memop=%d, "
166 hdr, phwcdef->name, phwcdef->int_name, phwcdef->reg_num,
238 hwcdef[idx].reg_num = REGNO_ANY;
323 /* reg_num */
336 hwcdef[idx].reg_num = reg;
  /src/external/gpl3/gdb.old/dist/gdb/
hppa-tdep.c 1590 unsigned int reg_num;
1633 reg_num = inst_saves_gr (inst);
1634 save_gr &= ~(1 << reg_num);
1646 if (reg_num >= (gdbarch_ptr_bit (gdbarch) == 64 ? 19 : 23)
1647 && reg_num <= 26)
1649 while (reg_num >= (gdbarch_ptr_bit (gdbarch) == 64 ? 19 : 23)
1650 && reg_num <= 26)
1657 reg_num = inst_saves_gr (inst);
1663 reg_num = inst_saves_fr (inst);
1664 save_fr &= ~(1 << reg_num);
1587 unsigned int reg_num; local
    [all...]
  /src/external/gpl3/gdb/dist/gdb/
hppa-tdep.c 1590 unsigned int reg_num;
1633 reg_num = inst_saves_gr (inst);
1634 save_gr &= ~(1 << reg_num);
1646 if (reg_num >= (gdbarch_ptr_bit (gdbarch) == 64 ? 19 : 23)
1647 && reg_num <= 26)
1649 while (reg_num >= (gdbarch_ptr_bit (gdbarch) == 64 ? 19 : 23)
1650 && reg_num <= 26)
1657 reg_num = inst_saves_gr (inst);
1663 reg_num = inst_saves_fr (inst);
1664 save_fr &= ~(1 << reg_num);
1587 unsigned int reg_num; local
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dce120/
amdgpu_hw_factory_dce120.c 48 #define reg_num 0 macro
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dcn10/
amdgpu_hw_factory_dcn10.c 49 #define reg_num 0 macro
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dcn20/
amdgpu_hw_factory_dcn20.c 55 #define reg_num 0 macro

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