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    Searched refs:reg_offsets (Results 1 - 10 of 10) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce80/
amdgpu_dce80_hw_sequencer.c 48 static const struct dce80_hw_seq_reg_offsets reg_offsets[] __unused = {
70 (reg + reg_offsets[id].crtc)
amdgpu_dce80_timing_generator.c 56 static const struct dce110_timing_generator_offsets reg_offsets[] = { variable in typeref:struct:dce110_timing_generator_offsets
238 tg110->derived_offsets = reg_offsets[instance];
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce100/
amdgpu_dce100_hw_sequencer.c 48 static const struct dce100_hw_seq_reg_offsets reg_offsets[] = { variable in typeref:struct:dce100_hw_seq_reg_offsets
70 (reg + reg_offsets[id].crtc)
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce112/
amdgpu_dce112_hw_sequencer.c 47 static const struct dce112_hw_seq_reg_offsets reg_offsets[] = { variable in typeref:struct:dce112_hw_seq_reg_offsets
68 (reg + reg_offsets[id].crtc)
amdgpu_dce112_compressor.c 51 static const struct dce112_compressor_reg_offsets reg_offsets[] = { variable in typeref:struct:dce112_compressor_reg_offsets
410 cp110->offsets = reg_offsets[params->inst];
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/
amdgpu_dce120_hw_sequencer.c 58 static const struct dce120_hw_seq_reg_offsets reg_offsets[] __unused = {
80 (reg + reg_offsets[id].crtc)
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/
amdgpu_dce110_compressor.c 52 static const struct dce110_compressor_reg_offsets reg_offsets[] = { variable in typeref:struct:dce110_compressor_reg_offsets
86 cp110->offsets = reg_offsets[crtc_inst];
312 cp110->offsets = reg_offsets[params->inst];
amdgpu_dce110_hw_sequencer.c 96 static const struct dce110_hw_seq_reg_offsets reg_offsets[] = { variable in typeref:struct:dce110_hw_seq_reg_offsets
112 (reg + reg_offsets[id].blnd)
115 (reg + reg_offsets[id].crtc)
  /src/sys/external/bsd/drm2/dist/drm/i915/gt/
intel_lrc.c 974 static const u8 *reg_offsets(const struct intel_engine_cs *engine) function
1621 set_offsets(regs, reg_offsets(engine), engine, false);
4576 set_offsets(regs, reg_offsets(engine), engine, inhibit);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_hw_sequencer.c 822 inst_offset = reg_offsets[pipe_ctx->stream_res.tg->inst].fmt;

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