| /src/external/gpl3/gdb/dist/sim/mn10300/ |
| mn10300-sim.h | 12 typedef uint32_t reg_t; typedef
29 reg_t regs[32]; /* registers, d0-d3, a0-a3, sp, pc, mdr, psw,
34 reg_t fs[32]; /* FS0-31 */
40 reg_t exc_trigger_regs[32];
41 reg_t exc_suspend_regs[32];
|
| op_utils.c | 141 reg_t func = State.regs[0];
143 reg_t parm1 = State.regs[1];
144 reg_t parm2 = load_word (State.regs[REG_SP] + 12);
145 reg_t parm3 = load_word (State.regs[REG_SP] + 16);
146 reg_t parm4 = load_word (State.regs[REG_SP] + 20);
|
| interp.c | 335 reg_t reg = State.regs[rn];
528 FS2FPU (*(reg_t *)reg, *val);
545 FPU2FS (*val, *(reg_t *)reg);
679 static inline reg_t
|
| /src/external/gpl3/gdb.old/dist/sim/mn10300/ |
| mn10300-sim.h | 12 typedef uint32_t reg_t; typedef
29 reg_t regs[32]; /* registers, d0-d3, a0-a3, sp, pc, mdr, psw,
34 reg_t fs[32]; /* FS0-31 */
40 reg_t exc_trigger_regs[32];
41 reg_t exc_suspend_regs[32];
|
| op_utils.c | 141 reg_t func = State.regs[0];
143 reg_t parm1 = State.regs[1];
144 reg_t parm2 = load_word (State.regs[REG_SP] + 12);
145 reg_t parm3 = load_word (State.regs[REG_SP] + 16);
146 reg_t parm4 = load_word (State.regs[REG_SP] + 20);
|
| interp.c | 335 reg_t reg = State.regs[rn];
528 FS2FPU (*(reg_t *)reg, *val);
545 FPU2FS (*val, *(reg_t *)reg);
679 static inline reg_t
|
| /src/external/gpl3/gdb/dist/sim/v850/ |
| v850-sim.h | 17 typedef uint32_t reg_t; typedef
24 reg_t regs[32]; /* general-purpose registers */
25 reg_t sregs[32]; /* system registers, including psw */
26 reg_t pc;
28 reg_t mpu0_sregs[28]; /* mpu0 system registers */
29 reg_t mpu1_sregs[28]; /* mpu1 system registers */
30 reg_t fpu_sregs[28]; /* fpu system registers */
31 reg_t selID_sregs[7][32]; /* system registers, selID 1 through selID 7 */
37 reg_t psw_mask; /* only allow non-reserved bits to be set */
|
| simops.c | 1670 reg_t buf;
1761 reg_t buf;
1791 reg_t buf;
|
| /src/external/gpl3/gdb.old/dist/sim/v850/ |
| v850-sim.h | 17 typedef uint32_t reg_t; typedef
24 reg_t regs[32]; /* general-purpose registers */
25 reg_t sregs[32]; /* system registers, including psw */
26 reg_t pc;
28 reg_t mpu0_sregs[28]; /* mpu0 system registers */
29 reg_t mpu1_sregs[28]; /* mpu1 system registers */
30 reg_t fpu_sregs[28]; /* fpu system registers */
31 reg_t selID_sregs[7][32]; /* system registers, selID 1 thru selID 7 */
37 reg_t psw_mask; /* only allow non-reserved bits to be set */
|
| simops.c | 1670 reg_t buf;
1761 reg_t buf;
1791 reg_t buf;
|
| /src/external/gpl3/gdb/dist/sim/d10v/ |
| d10v-sim.h | 31 typedef uint16_t reg_t; typedef
227 reg_t regs[16]; /* general-purpose registers */
235 reg_t cregs[16]; /* control registers */
240 reg_t sp[2]; /* holding area for SPI(0)/SPU(1) */
310 #define SET_PSW_BIT(MASK,VAL) move_to_cr (sd, cpu, PSW_CR, ~((reg_t) MASK), (VAL) ? (MASK) : 0, 1)
481 extern reg_t move_to_cr (SIM_DESC, SIM_CPU *, int cr, reg_t mask, reg_t val, int psw_hw_p);
|
| simops.c | 69 reg_t
70 move_to_cr (SIM_DESC sd, SIM_CPU *cpu, int cr, reg_t mask, reg_t val, int psw_hw_p)
1021 SET_PSW_F0 ((GPR (OP[0]) == (reg_t) SEXT4 (OP[1])) ? 1 : 0);
1031 SET_PSW_F0 ((GPR (OP[0]) == (reg_t)OP[1]) ? 1 : 0);
1071 SET_PSW_F0 ((GPR (OP[0]) < (reg_t)OP[1]) ? 1 : 0);
3368 reg_t buf;
3454 reg_t buf;
|
| /src/external/gpl3/gdb.old/dist/sim/d10v/ |
| d10v-sim.h | 31 typedef uint16_t reg_t; typedef
227 reg_t regs[16]; /* general-purpose registers */
235 reg_t cregs[16]; /* control registers */
240 reg_t sp[2]; /* holding area for SPI(0)/SPU(1) */
310 #define SET_PSW_BIT(MASK,VAL) move_to_cr (sd, cpu, PSW_CR, ~((reg_t) MASK), (VAL) ? (MASK) : 0, 1)
481 extern reg_t move_to_cr (SIM_DESC, SIM_CPU *, int cr, reg_t mask, reg_t val, int psw_hw_p);
|
| simops.c | 69 reg_t
70 move_to_cr (SIM_DESC sd, SIM_CPU *cpu, int cr, reg_t mask, reg_t val, int psw_hw_p)
1021 SET_PSW_F0 ((GPR (OP[0]) == (reg_t) SEXT4 (OP[1])) ? 1 : 0);
1031 SET_PSW_F0 ((GPR (OP[0]) == (reg_t)OP[1]) ? 1 : 0);
1071 SET_PSW_F0 ((GPR (OP[0]) < (reg_t)OP[1]) ? 1 : 0);
3368 reg_t buf;
3454 reg_t buf;
|
| /src/external/gpl3/binutils/dist/gas/config/ |
| bfin-defs.h | 339 typedef long reg_t; typedef
344 reg_t regno; /* Register ID as defined in machine_registers. */
|
| /src/external/gpl3/binutils.old/dist/gas/config/ |
| bfin-defs.h | 339 typedef long reg_t; typedef
344 reg_t regno; /* Register ID as defined in machine_registers. */
|
| /src/external/gpl3/gdb/dist/sim/cr16/ |
| cr16-sim.h | 49 typedef uint16_t reg_t; typedef
217 reg_t sp[2]; /* holding area for SPI(0)/SPU(1) */
|
| simops.c | 5282 reg_t buf;
5385 reg_t buf;
|
| /src/external/gpl3/gdb.old/dist/sim/cr16/ |
| cr16-sim.h | 49 typedef uint16_t reg_t; typedef
217 reg_t sp[2]; /* holding area for SPI(0)/SPU(1) */
|
| simops.c | 5282 reg_t buf;
5385 reg_t buf;
|
| /src/sys/lib/libunwind/ |
| Registers.hpp | 758 typedef uint64_t reg_t; typedef in class:_Unwind::Registers_SPARC64
822 typedef uint32_t reg_t; typedef in class:_Unwind::Registers_SPARC
|
| DwarfParser.hpp | 495 results->savedRegisters[reg].value = (reg - 16) * sizeof(typename R::reg_t);
|
| /src/external/gpl3/gdb/dist/gdb/ |
| arm-tdep.c | 12609 uint32_t bits_a, bit_c, bit_l, reg_t, reg_v;
12612 reg_t = bits (arm_insn_r->arm_insn, 12, 15);
12621 record_buf[0] = reg_t;
12629 record_buf[0] = reg_t;
12635 if (reg_t == 15)
12636 reg_t = ARM_PS_REGNUM;
12638 record_buf[0] = reg_t;
13138 uint32_t reg_t[2];
13140 reg_t[0] = bits (arm_insn_r->arm_insn, 12, 15);
13141 reg_t[1] = bits (arm_insn_r->arm_insn, 16, 19)
12608 uint32_t bits_a, bit_c, bit_l, reg_t, reg_v; local
13137 uint32_t reg_t[2]; local
[all...] |
| /src/external/gpl3/gdb.old/dist/gdb/ |
| arm-tdep.c | 12613 uint32_t bits_a, bit_c, bit_l, reg_t, reg_v;
12616 reg_t = bits (arm_insn_r->arm_insn, 12, 15);
12625 record_buf[0] = reg_t;
12633 record_buf[0] = reg_t;
12639 if (reg_t == 15)
12640 reg_t = ARM_PS_REGNUM;
12642 record_buf[0] = reg_t;
13142 uint32_t reg_t[2];
13144 reg_t[0] = bits (arm_insn_r->arm_insn, 12, 15);
13145 reg_t[1] = bits (arm_insn_r->arm_insn, 16, 19)
12612 uint32_t bits_a, bit_c, bit_l, reg_t, reg_v; local
13141 uint32_t reg_t[2]; local
[all...] |
