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  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_dsc.c 38 static void dsc_init_reg_values(struct dsc_reg_values *reg_vals);
39 static void dsc_update_from_dsc_parameters(struct dsc_reg_values *reg_vals, const struct dsc_parameters *dsc_params);
40 static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals);
176 return dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, &dsc_optc_cfg);
200 is_config_ok = dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, dsc_optc_cfg);
203 dsc_log_pps(dsc, &dsc20->reg_vals.pps);
204 dsc_write_to_registers(dsc, &dsc20->reg_vals);
472 static void dsc_init_reg_values(struct dsc_reg_values *reg_vals)
476 memset(reg_vals, 0, sizeof(struct dsc_reg_values));
479 reg_vals->dsc_clock_enable = 1
    [all...]
dcn20_dsc.h 561 struct dsc_reg_values reg_vals; member in struct:dcn20_dsc

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