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Searched
refs:res_cap
(Results
1 - 13
of
13
) sorted by relevancy
/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce80/
amdgpu_dce80_resource.c
367
static const struct resource_caps
res_cap
= {
variable in typeref:typename:const struct resource_caps
806
for (i = 0; i < pool->base.
res_cap
->num_ddc; i++) {
935
pool->base.
res_cap
= &
res_cap
;
943
pool->base.pipe_count =
res_cap
.num_timing_generator;
944
pool->base.timing_generator_count =
res_cap
.num_timing_generator;
1060
for (i = 0; i < pool->base.
res_cap
->num_ddc; i++) {
1133
pool->base.
res_cap
= &res_cap_81;
1257
for (i = 0; i < pool->base.
res_cap
->num_ddc; i++) {
1330
pool->base.
res_cap
= &res_cap_83
[
all
...]
/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce100/
amdgpu_dce100_resource.c
366
static const struct resource_caps
res_cap
= {
variable in typeref:typename:const struct resource_caps
758
for (i = 0; i < pool->base.
res_cap
->num_ddc; i++) {
969
pool->base.
res_cap
= &
res_cap
;
1044
pool->base.pipe_count =
res_cap
.num_timing_generator;
1045
pool->base.timing_generator_count = pool->base.
res_cap
->num_timing_generator;
1098
for (i = 0; i < pool->base.
res_cap
->num_ddc; i++) {
/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/
amdgpu_dce120_resource.c
497
static const struct resource_caps
res_cap
= {
variable in typeref:typename:const struct resource_caps
624
for (i = 0; i < pool->base.
res_cap
->num_ddc; i++) {
1047
pool->base.
res_cap
= &
res_cap
;
1051
pool->base.pipe_count =
res_cap
.num_timing_generator;
1052
pool->base.timing_generator_count = pool->base.
res_cap
->num_timing_generator;
1195
for (i = 0; i < pool->base.
res_cap
->num_ddc; i++) {
/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/
amdgpu_dcn21_resource.c
880
for (i = 0; i < pool->base.
res_cap
->num_dsc; i++) {
910
for (i = 0; i < pool->base.
res_cap
->num_ddc; i++) {
923
for (i = 0; i < pool->base.
res_cap
->num_opp; i++) {
928
for (i = 0; i < pool->base.
res_cap
->num_timing_generator; i++) {
935
for (i = 0; i < pool->base.
res_cap
->num_dwb; i++) {
1345
dcn2_1_ip.max_num_otg = pool->base.
res_cap
->num_timing_generator;
1675
pool->base.
res_cap
= &res_cap_rn;
1678
//pool->base.
res_cap
= &res_cap_nv10_FPGA_2pipe_dsc;
1679
pool->base.
res_cap
= &res_cap_rn_FPGA_4pipe;
1690
pool->base.pipe_count = pool->base.
res_cap
->num_timing_generator
[
all
...]
/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_resource.c
531
static const struct resource_caps
res_cap
= {
variable in typeref:typename:const struct resource_caps
975
for (i = 0; i < pool->base.
res_cap
->num_ddc; i++) {
1328
pool->base.
res_cap
= &rv2_res_cap;
1330
pool->base.
res_cap
= &
res_cap
;
1344
pool->base.pipe_count = pool->base.
res_cap
->num_timing_generator;
1543
for (i = 0; i < pool->base.
res_cap
->num_ddc; i++) {
amdgpu_dcn10_hw_sequencer.c
397
for (i = 0; i < pool->
res_cap
->num_dsc; i++) {
1172
for (i = 0; i < dc->res_pool->
res_cap
->num_opp; i++) {
1321
for (i = 0; i < res_pool->
res_cap
->num_dsc; i++)
/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_resource.c
1325
for (i = 0; i < pool->base.
res_cap
->num_dsc; i++) {
1355
for (i = 0; i < pool->base.
res_cap
->num_ddc; i++) {
1368
for (i = 0; i < pool->base.
res_cap
->num_opp; i++) {
1373
for (i = 0; i < pool->base.
res_cap
->num_timing_generator; i++) {
1380
for (i = 0; i < pool->base.
res_cap
->num_dwb; i++) {
1550
if (pool->
res_cap
->num_dsc == pool->
res_cap
->num_opp) {
1557
for (i = 0; i < pool->
res_cap
->num_dsc; i++)
1571
for (i = 0; i < pool->
res_cap
->num_dsc; i++)
3070
uint32_t pipe_count = pool->
res_cap
->num_dwb
[
all
...]
amdgpu_dcn20_hwseq.c
299
ASSERT(opp_id_src0 < dc->res_pool->
res_cap
->num_opp);
304
ASSERT(opp_id_src1 < dc->res_pool->
res_cap
->num_opp);
2343
for (i = 0; i < dc->res_pool->
res_cap
->num_opp; i++) {
2378
for (i = 0; i < res_pool->
res_cap
->num_dwb; i++)
/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/
core_types.h
220
const struct resource_caps *
res_cap
;
member in struct:resource_pool
/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/
amdgpu_dce110_resource.c
815
for (i = 0; i < pool->base.
res_cap
->num_ddc; i++) {
1334
pool->base.
res_cap
= dce110_resource_cap(&ctx->asic_id);
1341
pool->base.pipe_count = pool->base.
res_cap
->num_timing_generator;
1343
pool->base.timing_generator_count = pool->base.
res_cap
->num_timing_generator;
1456
for (i = 0; i < pool->base.
res_cap
->num_ddc; i++) {
/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce112/
amdgpu_dce112_resource.c
776
for (i = 0; i < pool->base.
res_cap
->num_ddc; i++) {
1203
pool->base.
res_cap
= dce112_resource_cap(&ctx->asic_id);
1210
pool->base.pipe_count = pool->base.
res_cap
->num_timing_generator;
1211
pool->base.timing_generator_count = pool->base.
res_cap
->num_timing_generator;
1342
for (i = 0; i < pool->base.
res_cap
->num_ddc; i++) {
/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
amdgpu_dce_i2c_hw.c
387
if (line < pool->
res_cap
->num_ddc)
/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/
amdgpu_dc_resource.c
246
const struct resource_caps *caps = pool->
res_cap
;
2077
return dc->res_pool->
res_cap
->num_dsc > 0;
Completed in 29 milliseconds
Indexes created Sat Oct 18 17:09:52 GMT 2025