| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_hwseq.c | 71 if (dc->res_pool->gsl_groups.gsl_0 == 0)
73 if (dc->res_pool->gsl_groups.gsl_1 == 0)
75 if (dc->res_pool->gsl_groups.gsl_2 == 0)
121 dc->res_pool->gsl_groups.gsl_0 = 1;
125 dc->res_pool->gsl_groups.gsl_1 = 1;
129 dc->res_pool->gsl_groups.gsl_2 = 1;
147 dc->res_pool->gsl_groups.gsl_0 = 0;
151 dc->res_pool->gsl_groups.gsl_1 = 0;
155 dc->res_pool->gsl_groups.gsl_2 = 0;
299 ASSERT(opp_id_src0 < dc->res_pool->res_cap->num_opp)
2293 struct resource_pool *res_pool = dc->res_pool; local in function:dcn20_fpga_init_hw
[all...] |
| amdgpu_dcn20_resource.c | 1587 const struct resource_pool *pool = dc->res_pool;
1590 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1625 release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc);
1837 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1892 for (i = 0, pipe_cnt = -1; i < dc->res_pool->pipe_count; i++) {
1908 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1924 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
2198 dc->res_pool->funcs->populate_dml_writeback_from_context(dc, res_ctx, pipes);
2244 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2290 for (i = 0; i < dc->res_pool->pipe_count; i++)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_hw_sequencer.c | 81 const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000;
98 for (i = 0; i < dc->res_pool->pipe_count; i++) {
138 dc->res_pool->hubbub->funcs->wm_read_state(dc->res_pool->hubbub, &wm);
162 struct resource_pool *pool = dc->res_pool;
277 struct resource_pool *pool = dc->res_pool;
662 struct hubp *hubp = dc->res_pool->hubps[0];
682 struct hubp *hubp = dc->res_pool->hubps[0];
691 for (i = 0; i < dc->res_pool->pipe_count; i++) {
692 if (!dc->res_pool->hubps[i]->power_gated
1246 struct resource_pool *res_pool = dc->res_pool; local in function:dcn10_init_hw
[all...] |
| amdgpu_dcn10_hw_sequencer_debug.c | 85 const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000;
89 dc->res_pool->hubbub->funcs->wm_read_state(dc->res_pool->hubbub, &wm);
117 struct resource_pool *pool = dc->res_pool;
123 const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000;
195 struct resource_pool *pool = dc->res_pool;
237 struct resource_pool *pool = dc->res_pool;
294 struct resource_pool *pool = dc->res_pool;
334 struct resource_pool *pool = dc->res_pool;
389 struct resource_pool *pool = dc->res_pool;
[all...] |
| dcn10_hw_sequencer.h | 149 struct resource_pool *res_pool,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce100/ |
| amdgpu_dce100_hw_sequencer.c | 117 dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool);
129 dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/ |
| amdgpu_dcn21_hwseq.c | 85 return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config);
|
| amdgpu_dcn21_resource.c | 1060 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1064 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
1089 if (dc->res_pool->funcs->populate_dml_pipes)
1090 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
1139 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
1341 struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool);
1635 for (i = 0; i < dc->res_pool->pipe_count; i++) {
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/ |
| amdgpu_dc.c | 722 dc->res_pool = dc_create_resource_pool(dc, init_params, dc_ctx->dce_version);
723 if (!dc->res_pool)
726 dc->clk_mgr = dc_clk_mgr_create(dc->ctx, dc->res_pool->pp_smu, dc->res_pool->dccg);
730 if (dc->res_pool->funcs->update_bw_bounding_box)
731 dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params);
780 for (i = 0; i < dc->res_pool->pipe_count; i++) {
856 full_pipe_count = dc->res_pool->pipe_count;
857 if (dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE)
861 dc->res_pool->stream_enc_count)
[all...] |
| amdgpu_dc_resource.c | 127 struct resource_pool *res_pool = NULL; local in function:dc_create_resource_pool
131 res_pool = dce80_create_resource_pool(
135 res_pool = dce81_create_resource_pool(
139 res_pool = dce83_create_resource_pool(
143 res_pool = dce100_create_resource_pool(
147 res_pool = dce110_create_resource_pool(
153 res_pool = dce112_create_resource_pool(
158 res_pool = dce120_create_resource_pool(
165 res_pool = dcn10_create_resource_pool(init_data, dc);
170 res_pool = dcn20_create_resource_pool(init_data, dc)
[all...] |
| amdgpu_dc_debug.c | 319 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
323 for (i = 0; i < dc->res_pool->pipe_count; i++) {
335 for (i = 0; i < dc->res_pool->pipe_count; i++) {
|
| amdgpu_dc_surface.c | 160 for (i = 0; i < dc->res_pool->pipe_count; i++) {
172 for (i = 0; i < dc->res_pool->pipe_count; i++) {
|
| amdgpu_dc_link.c | 441 struct audio_support *aud_support = &link->dc->res_pool->audio_support;
759 struct audio_support *aud_support = &link->dc->res_pool->audio_support;
1280 if (link->dc->res_pool->funcs->link_init)
1281 link->dc->res_pool->funcs->link_init(link);
1358 link->link_enc = link->dc->res_pool->funcs->link_enc_create(
2326 struct abm *abm = link->ctx->dc->res_pool->abm;
2339 struct abm *abm = dc->res_pool->abm;
2340 struct dmcu *dmcu = dc->res_pool->dmcu;
2392 struct abm *abm = dc->res_pool->abm;
2405 struct dmcu *dmcu = dc->res_pool->dmcu
[all...] |
| amdgpu_dc_link_hwss.c | 104 struct dmcu *dmcu = dc->res_pool->dmcu;
109 link->dc->res_pool->dp_clock_source;
216 struct dmcu *dmcu = dc->res_pool->dmcu;
|
| amdgpu_dc_stream.c | 396 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
416 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
427 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
|
| amdgpu_dc_link_ddc.c | 664 if (ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout)
666 ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout(ddc, timeout);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/ |
| amdgpu_dce110_hw_sequencer.c | 208 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
1437 for (i = 0; i < dc->res_pool->stream_enc_count; i++) {
1438 dc->res_pool->stream_enc[i]->funcs->dp_blank(
1439 dc->res_pool->stream_enc[i]);
1462 for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
1463 dc->res_pool->timing_generators[i]->funcs->disable_crtc(
1464 dc->res_pool->timing_generators[i]);
1472 if (dc->res_pool->dp_clock_source->funcs->cs_power_down(
1473 dc->res_pool->dp_clock_source) == false)
1476 for (i = 0; i < dc->res_pool->clk_src_count; i++)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn10/ |
| amdgpu_rv1_clk_mgr_vbios_smu.c | 97 struct dmcu *dmcu = dc->res_pool->dmcu;
|
| amdgpu_rv1_clk_mgr.c | 106 for (i = 0; i < dc->res_pool->pipe_count; i++) {
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn21/ |
| amdgpu_rn_clk_mgr_vbios_smu.c | 91 struct dmcu *dmcu = dc->res_pool->dmcu;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce112/ |
| amdgpu_dce112_clk_mgr.c | 81 struct dmcu *dmcu = dc->res_pool->dmcu;
135 struct dmcu *dmcu = dc->res_pool->dmcu;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn20/ |
| amdgpu_dcn20_clk_mgr.c | 114 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
164 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
180 if (dc->res_pool->pp_smu)
181 pp_smu = &dc->res_pool->pp_smu->nv_funcs;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/ |
| hw_sequencer.h | 76 struct resource_pool *res_pool,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| amdgpu_dce_aux.c | 446 struct dce_aux *aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en];
568 aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en];
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce100/ |
| amdgpu_dce_clk_mgr.c | 242 struct dmcu *dmcu = clk_mgr_dce->base.ctx->dc->res_pool->dmcu;
|
