| /src/sys/external/bsd/drm2/dist/drm/i915/gt/ |
| intel_gt_pm_irq.h | 22 void gen6_gt_pm_reset_iir(struct intel_gt *gt, u32 reset_mask);
|
| intel_gt_pm_irq.c | 67 void gen6_gt_pm_reset_iir(struct intel_gt *gt, u32 reset_mask)
74 intel_uncore_write(uncore, reg, reset_mask);
75 intel_uncore_write(uncore, reg, reset_mask);
|
| /src/sys/arch/arm/amlogic/ |
| meson_resets.c | 42 #define RESET_MASK(index) __BIT((index) % 32)
86 const uint32_t reset_mask = RESET_MASK(index); local
89 RESET_WRITE(sc, reset_reg, val & ~reset_mask);
101 const uint32_t reset_mask = RESET_MASK(index); local
104 RESET_WRITE(sc, reset_reg, val | reset_mask);
|
| /src/sys/arch/arm/sunxi/ |
| sunxi_resets.c | 42 #define RESET_MASK(index) __BIT((index) % 32)
82 const uint32_t reset_mask = RESET_MASK(index); local
85 RESET_WRITE(sc, reset_reg, val & ~reset_mask);
97 const uint32_t reset_mask = RESET_MASK(index); local
100 RESET_WRITE(sc, reset_reg, val | reset_mask);
|
| /src/external/gpl3/gdb.old/dist/sim/frv/ |
| registers.h | 33 USI reset_mask; /* bits which are reset */ member in struct:__anon22219
|
| registers.c | 6473 mask = spr_control->reset_mask;
6482 mask = spr_control->reset_mask;
|
| /src/external/gpl3/gdb/dist/sim/frv/ |
| registers.h | 33 USI reset_mask; /* bits which are reset */ member in struct:__anon1694
|
| registers.c | 6473 mask = spr_control->reset_mask;
6482 mask = spr_control->reset_mask;
|
| /src/external/gpl3/gcc/dist/libsanitizer/sanitizer_common/ |
| sanitizer_mutex.h | 174 u64 reset_mask = ~0ull; local
181 new_state = (state | kWriterLock) & reset_mask;
185 new_state = (state + kWaitingWriterInc) & reset_mask;
211 reset_mask = ~kWriterSpinWait;
261 u64 reset_mask = ~0ull; local
267 new_state = (state + kReaderLockInc) & reset_mask;
269 new_state = (state + kWaitingReaderInc) & reset_mask;
291 reset_mask = ~kReaderSpinWait;
|
| /src/external/gpl3/gcc.old/dist/libsanitizer/sanitizer_common/ |
| sanitizer_mutex.h | 172 u64 reset_mask = ~0ull; local
179 new_state = (state | kWriterLock) & reset_mask;
183 new_state = (state + kWaitingWriterInc) & reset_mask;
209 reset_mask = ~kWriterSpinWait;
245 u64 reset_mask = ~0ull; local
251 new_state = (state + kReaderLockInc) & reset_mask;
253 new_state = (state + kWaitingReaderInc) & reset_mask;
275 reset_mask = ~kReaderSpinWait;
|
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_ni.c | 1755 u32 reset_mask = 0; local
1766 reset_mask |= RADEON_RESET_GFX;
1770 reset_mask |= RADEON_RESET_CP;
1773 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
1778 reset_mask |= RADEON_RESET_DMA;
1783 reset_mask |= RADEON_RESET_DMA1;
1788 reset_mask |= RADEON_RESET_DMA;
1791 reset_mask |= RADEON_RESET_DMA1;
1796 reset_mask |= RADEON_RESET_RLC;
1799 reset_mask |= RADEON_RESET_IH
1965 u32 reset_mask; local
2000 u32 reset_mask = cayman_gpu_check_soft_reset(rdev); local
[all...] |
| radeon_evergreen_dma.c | 178 u32 reset_mask = evergreen_gpu_check_soft_reset(rdev); local
180 if (!(reset_mask & RADEON_RESET_DMA)) {
|
| radeon_si_dma.c | 48 u32 reset_mask = si_gpu_check_soft_reset(rdev); local
56 if (!(reset_mask & mask)) {
|
| radeon_r600.c | 1651 u32 reset_mask = 0; local
1662 reset_mask |= RADEON_RESET_GFX;
1669 reset_mask |= RADEON_RESET_GFX;
1674 reset_mask |= RADEON_RESET_CP;
1677 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
1682 reset_mask |= RADEON_RESET_DMA;
1687 reset_mask |= RADEON_RESET_RLC;
1690 reset_mask |= RADEON_RESET_IH;
1693 reset_mask |= RADEON_RESET_SEM;
1696 reset_mask |= RADEON_RESET_GRBM
1917 u32 reset_mask; local
1957 u32 reset_mask = r600_gpu_check_soft_reset(rdev); local
[all...] |
| radeon_si.c | 3783 u32 reset_mask = 0; local
3794 reset_mask |= RADEON_RESET_GFX;
3798 reset_mask |= RADEON_RESET_CP;
3801 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
3806 reset_mask |= RADEON_RESET_RLC;
3811 reset_mask |= RADEON_RESET_DMA;
3816 reset_mask |= RADEON_RESET_DMA1;
3821 reset_mask |= RADEON_RESET_DMA;
3824 reset_mask |= RADEON_RESET_DMA1;
3830 reset_mask |= RADEON_RESET_IH
4096 u32 reset_mask; local
4136 u32 reset_mask = si_gpu_check_soft_reset(rdev); local
[all...] |
| radeon_ni_dma.c | 294 u32 reset_mask = cayman_gpu_check_soft_reset(rdev); local
302 if (!(reset_mask & mask)) {
|
| radeon_evergreen.c | 3833 u32 reset_mask = 0; local
3843 reset_mask |= RADEON_RESET_GFX;
3847 reset_mask |= RADEON_RESET_CP;
3850 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
3855 reset_mask |= RADEON_RESET_DMA;
3860 reset_mask |= RADEON_RESET_DMA;
3865 reset_mask |= RADEON_RESET_RLC;
3868 reset_mask |= RADEON_RESET_IH;
3871 reset_mask |= RADEON_RESET_SEM;
3874 reset_mask |= RADEON_RESET_GRBM
4058 u32 reset_mask; local
4098 u32 reset_mask = evergreen_gpu_check_soft_reset(rdev); local
[all...] |
| radeon_r600_dma.c | 215 u32 reset_mask = r600_gpu_check_soft_reset(rdev); local
217 if (!(reset_mask & RADEON_RESET_DMA)) {
|
| radeon_cik.c | 4871 u32 reset_mask = 0; local
4882 reset_mask |= RADEON_RESET_GFX;
4885 reset_mask |= RADEON_RESET_CP;
4890 reset_mask |= RADEON_RESET_RLC;
4895 reset_mask |= RADEON_RESET_DMA;
4900 reset_mask |= RADEON_RESET_DMA1;
4905 reset_mask |= RADEON_RESET_DMA;
4908 reset_mask |= RADEON_RESET_DMA1;
4914 reset_mask |= RADEON_RESET_IH;
4917 reset_mask |= RADEON_RESET_SEM
5238 u32 reset_mask; local
5278 u32 reset_mask = cik_gpu_check_soft_reset(rdev); local
[all...] |
| radeon_cik_sdma.c | 782 u32 reset_mask = cik_gpu_check_soft_reset(rdev); local
790 if (!(reset_mask & mask)) {
|
