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    Searched refs:ring_base (Results 1 - 4 of 4) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/i915/gvt/
scheduler.c 221 u32 ring_base = dev_priv->engine[ring_id]->mmio_base; local
224 reg = RING_INSTDONE(ring_base);
226 reg = RING_ACTHD(ring_base);
228 reg = RING_ACTHD_UDW(ring_base);
577 u32 ring_base; local
579 ring_base = dev_priv->engine[workload->ring_id]->mmio_base;
580 vgpu_vreg_t(vgpu, RING_START(ring_base)) = workload->rb_start;
799 u32 ring_base; local
819 ring_base = dev_priv->engine[workload->ring_id]->mmio_base;
820 vgpu_vreg_t(vgpu, RING_TAIL(ring_base)) = tail
    [all...]
handlers.c 523 u32 ring_base; local
533 ring_base = dev_priv->engine[ring_id]->mmio_base;
536 reg_nonpriv == i915_mmio_reg_offset(RING_NOPID(ring_base))) {
1664 u32 ring_base; local
1674 ring_base = dev_priv->engine[ring_id]->mmio_base;
1677 offset == i915_mmio_reg_offset(RING_TIMESTAMP(ring_base)) ||
1678 offset == i915_mmio_reg_offset(RING_TIMESTAMP_UDW(ring_base))) {
cmd_parser.c 846 u32 ring_base; local
858 ring_base = dev_priv->engine[s->ring_id]->mmio_base;
859 nopid = i915_mmio_reg_offset(RING_NOPID(ring_base));
  /src/sys/dev/pci/qat/
qat.c 1014 uint64_t ring_base; local
1097 ring_base = ETR_RING_BASE_BUILD(qr->qr_ring_paddr, qr->qr_ring_size);
1098 qat_etr_bank_ring_base_write_8(sc, bank, ring, ring_base);

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