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    Searched refs:rings (Results 1 - 14 of 14) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_test.c 54 if (adev->rings[i])
55 n -= adev->rings[i]->ring_size;
amdgpu_ring.c 46 * Rings
98 * This is the generic insert_nop function for rings except SDMA
113 * This is the generic pad_ib function for rings except SDMA
268 adev->rings[ring->idx] = ring;
345 DRM_ERROR("Failed to register debugfs file for rings !\n");
364 if (!(ring->adev) || !(ring->adev->rings[ring->idx]))
383 ring->adev->rings[ring->idx] = NULL;
397 * Helper for rings that don't support write and wait in a
amdgpu_fence.c 397 * Not all asics have all rings, so each asic will only
398 * start the fence driver on the rings it has.
501 * for all possible rings.
505 * Init the fence driver for all possible rings (all asics).
506 * Not all asics have all rings, so each asic will only
507 * start the fence driver on the rings it has using
521 * for all possible rings.
525 * Tear down the fence driver for all possible rings (all asics).
533 struct amdgpu_ring *ring = adev->rings[i];
559 * for all possible rings
    [all...]
amdgpu_ib.c 326 * amdgpu_ib_ring_tests - test IBs on the rings
363 struct amdgpu_ring *ring = adev->rings[i];
366 /* KIQ rings don't have an IB test because we never submit IBs
amdgpu_gmc.c 381 ring = adev->rings[i];
amdgpu_job.c 81 (*job)->base.sched = &adev->rings[0]->sched;
amdgpu_debugfs.c 970 struct amdgpu_ring *ring = adev->rings[i];
986 struct amdgpu_ring *ring = adev->rings[i];
1154 ring = adev->rings[val];
amdgpu.h 428 * CP & rings.
530 #define AMDGPU_MAX_WB 128 /* Reserve at most 128 WB slots for amdgpu-owned rings. */
872 /* rings */
875 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; member in struct:amdgpu_device
969 /* keep an lru list of rings by HW IP */
amdgpu_drv.c 566 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities
569 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))");
1222 /* wait for all rings to drain before suspending */
1224 struct amdgpu_ring *ring = adev->rings[i];
amdgpu_device.c 4013 struct amdgpu_ring *ring = adev->rings[i];
4318 struct amdgpu_ring *ring = tmp_adev->rings[i];
4394 struct amdgpu_ring *ring = tmp_adev->rings[i];
amdgpu_vm.c 1020 ring = adev->rings[i];
1022 /* only compute rings */
amdgpu_pm.c 3498 struct amdgpu_ring *ring = adev->rings[i];
  /src/sys/dev/ic/
dwc_gmac.c 274 * Allocate Tx and Rx rings
277 aprint_error_dev(sc->sc_dev, "could not allocate DMA rings\n");
588 void *rings; local
608 ringsize, &rings, BUS_DMA_NOWAIT | BUS_DMA_COHERENT);
615 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dma_ring_map, rings,
624 sc->sc_rxq.r_desc = rings;
627 /* and next rings to the TX side */
  /src/sys/external/bsd/drm2/dist/drm/i915/gvt/
cmd_parser.c 424 /* rings that support this cmd: BLT/RCS/VCS/VECS */
425 u16 rings; member in struct:cmd_info
660 if (opcode == e->info->opcode && e->info->rings & BIT(ring_id))
3038 unsigned int opcode, unsigned long rings)
3043 for_each_set_bit(ring, &rings, I915_NUM_ENGINES) {
3070 e->info->opcode, e->info->rings);
3082 gvt_dbg_cmd("add %-30s op %04x flag %x devs %02x rings %02x\n",
3084 e->info->devices, e->info->rings);

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