| /src/sys/arch/riscv/include/ |
| ieee.h | 3 #include <riscv/math.h> /* for #define __HAVE_LONG_DOUBLE 128 */
|
| bswap.h | 6 #include <riscv/byte_swap.h>
|
| ieeefp.h | 15 #include <riscv/fenv.h>
|
| pcb.h | 35 #include <riscv/reg.h>
|
| proc.h | 36 #include <riscv/vmparam.h>
41 * Machine-dependent part of the lwp structure for RISCV
|
| /src/sys/external/gpl2/dts/dist/arch/riscv/boot/dts/sophgo/ |
| sg2042-cpus.dtsi | 257 compatible = "thead,c920", "riscv";
259 riscv,isa = "rv64imafdc";
260 riscv,isa-base = "rv64i";
261 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
272 mmu-type = "riscv,sv39";
275 compatible = "riscv,cpu-intc";
282 compatible = "thead,c920", "riscv";
284 riscv,isa = "rv64imafdc";
285 riscv,isa-base = "rv64i";
286 riscv,isa-extensions = "i", "m", "a", "f", "d", "c"
[all...] |
| /src/share/installboot/ |
| Makefile | 6 SUBDIR= evbarm evbmips riscv
|
| /src/sys/arch/riscv/conf/ |
| std.riscv | 2 # $NetBSD: std.riscv,v 1.3 2025/01/01 17:53:07 skrll Exp $
4 machine riscv
|
| std.riscv64 | 4 machine riscv
|
| /src/share/installboot/riscv/ |
| Makefile | 9 FILESDIR= /usr/share/installboot/riscv
|
| /src/sys/external/gpl2/dts/dist/arch/riscv/boot/dts/allwinner/ |
| sun20i-d1s.dtsi | 15 compatible = "thead,c906", "riscv";
25 mmu-type = "riscv,sv39";
27 riscv,isa = "rv64imafdc";
28 riscv,isa-base = "rv64i";
29 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
34 compatible = "riscv,cpu-intc";
73 riscv,ndev = <175>;
80 compatible = "riscv,pmu";
81 riscv,event-to-mhpmcounters =
92 riscv,event-to-mhpmevent
[all...] |
| /src/lib/libc/arch/riscv/gen/ |
| fpgetmask.c | 41 #include <riscv/sysreg.h>
|
| fpsetmask.c | 41 #include <riscv/sysreg.h>
|
| fpgetround.c | 41 #include <riscv/sysreg.h>
|
| fpsetround.c | 41 #include <riscv/sysreg.h>
|
| fpgetsticky.c | 41 #include <riscv/sysreg.h>
|
| fpsetsticky.c | 42 #include <riscv/sysreg.h>
|
| /src/sys/external/gpl2/dts/dist/arch/riscv/boot/dts/sifive/ |
| fu540-c000.dtsi | 26 compatible = "sifive,e51", "sifive,rocket0", "riscv";
32 riscv,isa = "rv64imac";
33 riscv,isa-base = "rv64i";
34 riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
39 compatible = "riscv,cpu-intc";
44 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
56 mmu-type = "riscv,sv39";
58 riscv,isa = "rv64imafdc";
59 riscv,isa-base = "rv64i";
60 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr"
[all...] |
| fu740-c000.dtsi | 26 compatible = "sifive,bullet0", "riscv";
33 riscv,isa = "rv64imac";
34 riscv,isa-base = "rv64i";
35 riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
40 compatible = "riscv,cpu-intc";
45 compatible = "sifive,bullet0", "riscv";
57 mmu-type = "riscv,sv39";
60 riscv,isa = "rv64imafdc";
61 riscv,isa-base = "rv64i";
62 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr"
[all...] |
| /src/sys/external/gpl2/dts/dist/arch/riscv/boot/dts/microchip/ |
| mpfs.dtsi | 19 compatible = "sifive,e51", "sifive,rocket0", "riscv";
25 riscv,isa = "rv64imac";
26 riscv,isa-base = "rv64i";
27 riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
34 compatible = "riscv,cpu-intc";
40 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
52 mmu-type = "riscv,sv39";
54 riscv,isa = "rv64imafdc";
55 riscv,isa-base = "rv64i";
56 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr"
[all...] |
| /src/sys/arch/riscv/fdt/ |
| cpu_fdt.c | 39 #include <riscv/cpufunc.h>
40 #include <riscv/cpuvar.h>
41 #include <riscv/machdep.h>
42 #include <riscv/sbi.h>
44 #include <riscv/fdt/riscv_fdtvar.h>
|
| /src/sys/external/gpl2/dts/dist/arch/riscv/boot/dts/renesas/ |
| r9a07g043f.dtsi | 21 compatible = "andestech,ax45mp", "riscv";
26 riscv,isa = "rv64imafdc";
27 riscv,isa-base = "rv64i";
28 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
31 mmu-type = "riscv,sv39";
42 compatible = "andestech,cpu-intc", "riscv,cpu-intc";
136 riscv,ndev = <511>;
|
| /src/sys/arch/riscv/riscv/ |
| cpu_mainbus.c | 40 #include <riscv/locore.h>
|
| /src/distrib/utils/embedded/conf/ |
| riscv32.conf | 13 . ${DIR}/conf/riscv.conf
|
| riscv64.conf | 13 . ${DIR}/conf/riscv.conf
|
