1 /* $NetBSD: rk_gpio.c,v 1.8 2025/06/03 18:26:38 rjs Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: rk_gpio.c,v 1.8 2025/06/03 18:26:38 rjs Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/mutex.h> 38 #include <sys/kmem.h> 39 #include <sys/gpio.h> 40 #include <sys/bitops.h> 41 #include <sys/lwp.h> 42 43 #include <dev/fdt/fdtvar.h> 44 #include <dev/gpio/gpiovar.h> 45 46 #define GPIO_SWPORTA_DR_REG 0x0000 47 #define GPIO_SWPORTA_DDR_REG 0x0004 48 #define GPIO_INTEN_REG 0x0030 49 #define GPIO_INTMASK_REG 0x0034 50 #define GPIO_INTTYPE_LEVEL_REG 0x0038 51 #define GPIO_INT_POLARITY_REG 0x003c 52 #define GPIO_INT_STATUS_REG 0x0040 53 #define GPIO_INT_RAWSTATUS_REG 0x0044 54 #define GPIO_DEBOUNCE_REG 0x0048 55 #define GPIO_PORTA_EOI_REG 0x004c 56 #define GPIO_EXT_PORTA_REG 0x0050 57 #define GPIO_LS_SYNC_REG 0x0060 58 #define GPIO_VER_ID_REG 0x0078 59 #define GPIO_VER_ID_GPIOV2 0x0101157c 60 61 /* 62 * In "version 2" GPIO controllers, half of each register is used by the 63 * write_enable mask, so the 32 pins are spread over two registers. 64 * 65 * pins 0 - 15 go into the GPIO_SWPORT_*_L register 66 * pins 16 - 31 go into the GPIO_SWPORT_*_H register 67 */ 68 #define GPIOV2_SWPORT_DR_BASE 0x0000 69 #define GPIOV2_SWPORT_DR_REG(pin) \ 70 (GPIOV2_SWPORT_DR_BASE + GPIOV2_REG_OFFSET(pin)) 71 #define GPIOV2_SWPORT_DDR_BASE 0x0008 72 #define GPIOV2_SWPORT_DDR_REG(pin) \ 73 (GPIOV2_SWPORT_DDR_BASE + GPIOV2_REG_OFFSET(pin)) 74 #define GPIOV2_EXT_PORT_REG 0x0070 75 #define GPIOV2_REG_OFFSET(pin) (((pin) >> 4) << 2) 76 #define GPIOV2_DATA_MASK(pin) (__BIT((pin) & 0xF)) 77 #define GPIOV2_WRITE_MASK(pin) (__BIT(((pin) & 0xF) | 0x10)) 78 79 static const struct device_compatible_entry compat_data[] = { 80 { .compat = "rockchip,gpio-bank" }, 81 DEVICE_COMPAT_EOL 82 }; 83 84 struct rk_gpio_eint { 85 int (*eint_func)(void *); 86 void *eint_arg; 87 bool eint_mpsafe; 88 int eint_num; 89 }; 90 91 struct rk_gpio_softc { 92 device_t sc_dev; 93 bus_space_tag_t sc_bst; 94 bus_space_handle_t sc_bsh; 95 kmutex_t sc_lock; 96 97 struct gpio_chipset_tag sc_gp; 98 gpio_pin_t sc_pins[32]; 99 device_t sc_gpiodev; 100 101 void *sc_ih; 102 struct rk_gpio_eint sc_eint[32]; 103 }; 104 105 struct rk_gpio_pin { 106 struct rk_gpio_softc *pin_sc; 107 u_int pin_nr; 108 int pin_flags; 109 bool pin_actlo; 110 }; 111 112 #define RD4(sc, reg) \ 113 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 114 #define WR4(sc, reg, val) \ 115 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 116 117 static int rk_gpio_match(device_t, cfdata_t, void *); 118 static void rk_gpio_attach(device_t, device_t, void *); 119 120 CFATTACH_DECL_NEW(rk_gpio, sizeof(struct rk_gpio_softc), 121 rk_gpio_match, rk_gpio_attach, NULL, NULL); 122 123 static void * 124 rk_gpio_acquire(device_t dev, const void *data, size_t len, int flags) 125 { 126 struct rk_gpio_softc * const sc = device_private(dev); 127 struct rk_gpio_pin *gpin; 128 const u_int *gpio = data; 129 130 if (len != 12) 131 return NULL; 132 133 const uint8_t pin = be32toh(gpio[1]) & 0xff; 134 const bool actlo = be32toh(gpio[2]) & 1; 135 136 if (pin >= __arraycount(sc->sc_pins)) 137 return NULL; 138 139 sc->sc_gp.gp_pin_ctl(sc, pin, flags); 140 141 gpin = kmem_zalloc(sizeof(*gpin), KM_SLEEP); 142 gpin->pin_sc = sc; 143 gpin->pin_nr = pin; 144 gpin->pin_flags = flags; 145 gpin->pin_actlo = actlo; 146 147 return gpin; 148 } 149 150 static void 151 rk_gpio_release(device_t dev, void *priv) 152 { 153 struct rk_gpio_softc * const sc = device_private(dev); 154 struct rk_gpio_pin *pin = priv; 155 156 KASSERT(sc == pin->pin_sc); 157 158 sc->sc_gp.gp_pin_ctl(sc, pin->pin_nr, GPIO_PIN_INPUT); 159 160 kmem_free(pin, sizeof(*pin)); 161 } 162 163 static int 164 rk_gpio_read(device_t dev, void *priv, bool raw) 165 { 166 struct rk_gpio_softc * const sc = device_private(dev); 167 struct rk_gpio_pin *pin = priv; 168 int val; 169 170 KASSERT(sc == pin->pin_sc); 171 172 val = sc->sc_gp.gp_pin_read(sc, pin->pin_nr); 173 if (!raw && pin->pin_actlo) 174 val = !val; 175 176 return val; 177 } 178 179 static void 180 rk_gpio_write(device_t dev, void *priv, int val, bool raw) 181 { 182 struct rk_gpio_softc * const sc = device_private(dev); 183 struct rk_gpio_pin *pin = priv; 184 185 KASSERT(sc == pin->pin_sc); 186 187 if (!raw && pin->pin_actlo) 188 val = !val; 189 190 sc->sc_gp.gp_pin_write(sc, pin->pin_nr, val); 191 } 192 193 static struct fdtbus_gpio_controller_func rk_gpio_funcs = { 194 .acquire = rk_gpio_acquire, 195 .release = rk_gpio_release, 196 .read = rk_gpio_read, 197 .write = rk_gpio_write, 198 }; 199 200 static int 201 rk_gpio_pin_read(void *priv, int pin) 202 { 203 struct rk_gpio_softc * const sc = priv; 204 uint32_t data; 205 int val; 206 207 KASSERT(pin < __arraycount(sc->sc_pins)); 208 209 const uint32_t data_mask = __BIT(pin); 210 211 /* No lock required for reads */ 212 data = RD4(sc, GPIO_EXT_PORTA_REG); 213 val = __SHIFTOUT(data, data_mask); 214 215 return val; 216 } 217 218 static void 219 rk_gpio_pin_write(void *priv, int pin, int val) 220 { 221 struct rk_gpio_softc * const sc = priv; 222 uint32_t data; 223 224 KASSERT(pin < __arraycount(sc->sc_pins)); 225 226 const uint32_t data_mask = __BIT(pin); 227 228 mutex_enter(&sc->sc_lock); 229 data = RD4(sc, GPIO_SWPORTA_DR_REG); 230 if (val) 231 data |= data_mask; 232 else 233 data &= ~data_mask; 234 WR4(sc, GPIO_SWPORTA_DR_REG, data); 235 mutex_exit(&sc->sc_lock); 236 } 237 238 static void 239 rk_gpio_pin_ctl(void *priv, int pin, int flags) 240 { 241 struct rk_gpio_softc * const sc = priv; 242 uint32_t ddr; 243 244 KASSERT(pin < __arraycount(sc->sc_pins)); 245 246 mutex_enter(&sc->sc_lock); 247 ddr = RD4(sc, GPIO_SWPORTA_DDR_REG); 248 if (flags & GPIO_PIN_INPUT) 249 ddr &= ~__BIT(pin); 250 else if (flags & GPIO_PIN_OUTPUT) 251 ddr |= __BIT(pin); 252 WR4(sc, GPIO_SWPORTA_DDR_REG, ddr); 253 mutex_exit(&sc->sc_lock); 254 } 255 256 static int 257 rk_gpio_v2_pin_read(void *priv, int pin) 258 { 259 struct rk_gpio_softc * const sc = priv; 260 uint32_t data; 261 int val; 262 263 KASSERT(pin < __arraycount(sc->sc_pins)); 264 265 const uint32_t data_mask = __BIT(pin); 266 267 /* No lock required for reads */ 268 data = RD4(sc, GPIOV2_EXT_PORT_REG); 269 val = __SHIFTOUT(data, data_mask); 270 271 return val; 272 } 273 274 static void 275 rk_gpio_v2_pin_write(void *priv, int pin, int val) 276 { 277 struct rk_gpio_softc * const sc = priv; 278 uint32_t data; 279 280 KASSERT(pin < __arraycount(sc->sc_pins)); 281 282 const uint32_t write_mask = GPIOV2_WRITE_MASK(pin); 283 284 /* No lock required for writes on v2 controllers */ 285 data = val ? GPIOV2_DATA_MASK(pin) : 0; 286 WR4(sc, GPIOV2_SWPORT_DR_REG(pin), write_mask | data); 287 } 288 289 static void 290 rk_gpio_v2_pin_ctl(void *priv, int pin, int flags) 291 { 292 struct rk_gpio_softc * const sc = priv; 293 uint32_t ddr; 294 295 KASSERT(pin < __arraycount(sc->sc_pins)); 296 297 /* No lock required for writes on v2 controllers */ 298 ddr = (flags & GPIO_PIN_OUTPUT) ? GPIOV2_DATA_MASK(pin) : 0; 299 WR4(sc, GPIOV2_SWPORT_DDR_REG(pin), GPIOV2_WRITE_MASK(pin) | ddr); 300 } 301 302 static int 303 rk_gpio_intr(void *priv) 304 { 305 struct rk_gpio_softc * const sc = priv; 306 struct rk_gpio_eint *eint; 307 uint32_t status, bit; 308 int ret = 0; 309 310 status = RD4(sc, GPIO_INT_STATUS_REG); 311 if (status == 0) 312 return ret; 313 314 WR4(sc, GPIO_PORTA_EOI_REG, status); 315 316 while ((bit = ffs32(status)) != 0) { 317 status &= ~__BIT(bit - 1); 318 eint = &sc->sc_eint[bit - 1]; 319 if (eint == NULL || eint->eint_func == NULL) 320 continue; 321 if (!eint->eint_mpsafe) 322 KERNEL_LOCK(1, curlwp); 323 ret |= eint->eint_func(eint->eint_arg); 324 if (!eint->eint_mpsafe) 325 KERNEL_UNLOCK_ONE(curlwp); 326 } 327 328 return ret; 329 } 330 331 static void * 332 rk_intr_enable(struct rk_gpio_softc *sc, u_int pin, uint32_t level, 333 uint32_t polarity, bool mpsafe, int (*func)(void *), void *arg) 334 { 335 uint32_t val; 336 struct rk_gpio_eint *eint; 337 338 mutex_enter(&sc->sc_lock); 339 if (sc->sc_eint[pin].eint_func != NULL) { 340 mutex_exit(&sc->sc_lock); 341 return NULL; /* in use */ 342 } 343 344 eint = &sc->sc_eint[pin]; 345 346 eint->eint_func = func; 347 eint->eint_arg = arg; 348 eint->eint_mpsafe = mpsafe; 349 eint->eint_num = pin; 350 351 val = RD4(sc, GPIO_INTTYPE_LEVEL_REG); 352 if (level) 353 val |= 1 << pin; 354 else 355 val &= ~(1 << pin); 356 WR4(sc, GPIO_INTTYPE_LEVEL_REG, val); 357 358 val = RD4(sc, GPIO_INT_POLARITY_REG); 359 if (polarity) 360 val |= 1 << pin; 361 else 362 val &= ~(1 << pin); 363 WR4(sc, GPIO_INT_POLARITY_REG, val); 364 365 val = RD4(sc, GPIO_INTEN_REG); 366 val |= 1 << pin; 367 WR4(sc, GPIO_INTEN_REG, val); 368 #if 0 369 /* Configure eint mode */ 370 val = R4(sc, SUNXI_GPIO_INT_CFG, pin); 371 val &= ~SUNXI_GPIO_INT_MODEMASK(eint->eint_num); 372 val |= __SHIFTIN(mode, SUNXI_GPIO_INT_MODEMASK(eint->eint_num)); 373 GPIO_WRITE(sc, SUNXI_GPIO_INT_CFG(eint->eint_bank, eint->eint_num), val); 374 375 val = SUNXI_GPIO_INT_DEBOUNCE_CLK_SEL; 376 GPIO_WRITE(sc, SUNXI_GPIO_INT_DEBOUNCE(eint->eint_bank), val); 377 378 /* Enable eint */ 379 val = GPIO_READ(sc, SUNXI_GPIO_INT_CTL(eint->eint_bank)); 380 val |= __BIT(eint->eint_num); 381 GPIO_WRITE(sc, SUNXI_GPIO_INT_CTL(eint->eint_bank), val); 382 #endif 383 mutex_exit(&sc->sc_lock); 384 385 return eint; 386 } 387 388 static void 389 rk_intr_disable(struct rk_gpio_softc *sc, struct rk_gpio_eint *eint) 390 { 391 uint32_t val; 392 393 KASSERT(eint != NULL && eint->eint_func != NULL); 394 395 mutex_enter(&sc->sc_lock); 396 397 /* Disable eint */ 398 val = RD4(sc, GPIO_INTEN_REG); 399 val &= ~__BIT(eint->eint_num); 400 WR4(sc, GPIO_INTEN_REG, val); 401 WR4(sc, GPIO_INT_STATUS_REG, __BIT(eint->eint_num)); 402 403 sc->sc_eint[eint->eint_num].eint_func = NULL; 404 405 mutex_exit(&sc->sc_lock); 406 } 407 408 static void * 409 rk_fdt_intr_establish(device_t dev, u_int *specifier, int ipl, int flags, 410 int (*func)(void *), void *arg, const char *xname) 411 { 412 struct rk_gpio_softc * const sc = device_private(dev); 413 bool mpsafe = (flags & GPIO_INTR_MPSAFE) != 0; 414 uint32_t level, polarity; 415 416 const uint32_t pin = be32toh(specifier[0]); 417 const uint32_t type = be32toh(specifier[1]) & 0xf; 418 419 switch (type) { 420 case FDT_INTR_TYPE_POS_EDGE: 421 level = 1; 422 polarity = 1; 423 break; 424 case FDT_INTR_TYPE_NEG_EDGE: 425 level = 1; 426 polarity = 0; 427 break; 428 case FDT_INTR_TYPE_HIGH_LEVEL: 429 level = 0; 430 polarity = 1; 431 break; 432 case FDT_INTR_TYPE_LOW_LEVEL: 433 level = 0; 434 polarity = 0; 435 break; 436 default: 437 aprint_error_dev(dev, "%s: unsupported irq type 0x%x\n", 438 __func__, type); 439 return NULL; 440 } 441 442 return rk_intr_enable(sc, pin, level, polarity, mpsafe, func, arg); 443 } 444 445 static void 446 rk_fdt_intr_disestablish(device_t dev, void *ih) 447 { 448 struct rk_gpio_softc * const sc = device_private(dev); 449 struct rk_gpio_eint * const eint = ih; 450 451 rk_intr_disable(sc, eint); 452 } 453 454 static bool 455 rk_fdt_intrstr(device_t dev, u_int *specifier, char *buf, size_t buflen) 456 { 457 458 if (!specifier) 459 return false; 460 const u_int pin = be32toh(specifier[0]); 461 462 if (pin < 0 || pin >= 32) 463 return false; 464 465 snprintf(buf, buflen, "GPIO %d", pin); 466 467 return true; 468 } 469 470 static void 471 rk_fdt_intr_mask(device_t dev, void *ih) 472 { 473 struct rk_gpio_softc * const sc = device_private(dev); 474 void * const gpio = device_private(sc->sc_gpiodev); 475 476 gpio_intr_mask(gpio, ih); 477 } 478 479 static void 480 rk_fdt_intr_unmask(device_t dev, void *ih) 481 { 482 struct rk_gpio_softc * const sc = device_private(dev); 483 void * const gpio = device_private(sc->sc_gpiodev); 484 485 gpio_intr_unmask(gpio, ih); 486 } 487 488 489 static struct fdtbus_interrupt_controller_func rk_gpio_intrfuncs = { 490 .establish = rk_fdt_intr_establish, 491 .disestablish = rk_fdt_intr_disestablish, 492 .intrstr = rk_fdt_intrstr, 493 .mask = rk_fdt_intr_mask, 494 .unmask = rk_fdt_intr_unmask 495 }; 496 497 static void * 498 rk_gpio_intr_establish(void *vsc, int pin, int ipl, int irqmode, 499 int (*func)(void *), void *arg) 500 { 501 struct rk_gpio_softc * const sc = vsc; 502 bool mpsafe = (irqmode & GPIO_INTR_MPSAFE) != 0; 503 int type = irqmode & GPIO_INTR_MODE_MASK; 504 uint32_t level, polarity; 505 506 switch (type) { 507 case GPIO_INTR_POS_EDGE: 508 level = 1; 509 polarity = 1; 510 break; 511 case GPIO_INTR_NEG_EDGE: 512 level = 1; 513 polarity = 0; 514 break; 515 case GPIO_INTR_HIGH_LEVEL: 516 level = 0; 517 polarity = 1; 518 break; 519 case GPIO_INTR_LOW_LEVEL: 520 level = 0; 521 polarity = 0; 522 break; 523 default: 524 aprint_error_dev(sc->sc_dev, "%s: unsupported irq type 0x%x\n", 525 __func__, type); 526 return NULL; 527 } 528 529 return rk_intr_enable(sc, pin, level, polarity, mpsafe, func, arg); 530 } 531 532 static void 533 rk_gpio_intr_disestablish(void *vsc, void *ih) 534 { 535 struct rk_gpio_softc * const sc = vsc; 536 struct rk_gpio_eint * const eint = ih; 537 538 rk_intr_disable(sc, eint); 539 } 540 541 static bool 542 rk_gpio_intrstr(void *vsc, int pin, int irqmode, char *buf, size_t buflen) 543 { 544 545 if (pin < 0 || pin >= 32) 546 return false; 547 548 snprintf(buf, buflen, "GPIO %d", pin); 549 550 return true; 551 } 552 553 static void 554 rk_gpio_intr_mask(void *priv, void *ih) 555 { 556 struct rk_gpio_softc * const sc = priv; 557 struct rk_gpio_eint * const eint = ih; 558 uint32_t val; 559 560 val = RD4(sc, GPIO_INTMASK_REG); 561 val |= 1 << eint->eint_num; 562 WR4(sc, GPIO_INTEN_REG, val); 563 } 564 565 static void 566 rk_gpio_intr_unmask(void *priv, void *ih) 567 { 568 struct rk_gpio_softc * const sc = priv; 569 struct rk_gpio_eint * const eint = ih; 570 uint32_t val; 571 572 val = RD4(sc, GPIO_INTMASK_REG); 573 val &= ~(1 << eint->eint_num); 574 WR4(sc, GPIO_INTEN_REG, val); 575 } 576 577 static void 578 rk_gpio_attach_ports(struct rk_gpio_softc *sc) 579 { 580 struct gpiobus_attach_args gba; 581 u_int pin; 582 583 for (pin = 0; pin < __arraycount(sc->sc_pins); pin++) { 584 sc->sc_pins[pin].pin_num = pin; 585 sc->sc_pins[pin].pin_caps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT; 586 sc->sc_pins[pin].pin_state = rk_gpio_pin_read(sc, pin); 587 } 588 589 memset(&gba, 0, sizeof(gba)); 590 gba.gba_gc = &sc->sc_gp; 591 gba.gba_pins = sc->sc_pins; 592 gba.gba_npins = __arraycount(sc->sc_pins); 593 sc->sc_gpiodev = config_found(sc->sc_dev, &gba, NULL, CFARGS_NONE); 594 } 595 596 static int 597 rk_gpio_match(device_t parent, cfdata_t cf, void *aux) 598 { 599 struct fdt_attach_args * const faa = aux; 600 601 return of_compatible_match(faa->faa_phandle, compat_data); 602 } 603 604 static void 605 rk_gpio_attach(device_t parent, device_t self, void *aux) 606 { 607 struct rk_gpio_softc * const sc = device_private(self); 608 struct gpio_chipset_tag * const gp = &sc->sc_gp; 609 struct fdt_attach_args * const faa = aux; 610 const int phandle = faa->faa_phandle; 611 char intrstr[128]; 612 struct clk *clk; 613 bus_addr_t addr; 614 bus_size_t size; 615 uint32_t ver_id; 616 int ver; 617 618 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 619 aprint_error(": couldn't get registers\n"); 620 return; 621 } 622 623 if ((clk = fdtbus_clock_get_index(phandle, 0)) == NULL || clk_enable(clk) != 0) { 624 aprint_error(": couldn't enable clock\n"); 625 return; 626 } 627 628 sc->sc_dev = self; 629 sc->sc_bst = faa->faa_bst; 630 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 631 aprint_error(": couldn't map registers\n"); 632 return; 633 } 634 635 gp->gp_cookie = sc; 636 ver_id = RD4(sc, GPIO_VER_ID_REG); 637 switch (ver_id) { 638 case 0: /* VER_ID not implemented in v1 but reads back as 0 */ 639 ver = 1; 640 gp->gp_pin_read = rk_gpio_pin_read; 641 gp->gp_pin_write = rk_gpio_pin_write; 642 gp->gp_pin_ctl = rk_gpio_pin_ctl; 643 gp->gp_intr_establish = rk_gpio_intr_establish; 644 gp->gp_intr_disestablish = rk_gpio_intr_disestablish; 645 gp->gp_intr_str = rk_gpio_intrstr; 646 gp->gp_intr_mask = rk_gpio_intr_mask; 647 gp->gp_intr_unmask = rk_gpio_intr_unmask; 648 break; 649 case GPIO_VER_ID_GPIOV2: 650 ver = 2; 651 gp->gp_pin_read = rk_gpio_v2_pin_read; 652 gp->gp_pin_write = rk_gpio_v2_pin_write; 653 gp->gp_pin_ctl = rk_gpio_v2_pin_ctl; 654 /* XXX */ 655 break; 656 default: 657 aprint_error(": unknown version 0x%08" PRIx32 "\n", ver_id); 658 return; 659 } 660 661 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM); 662 663 aprint_naive("\n"); 664 aprint_normal(": GPIO v%d (%s)\n", ver, fdtbus_get_string(phandle, "name")); 665 666 fdtbus_register_gpio_controller(self, phandle, &rk_gpio_funcs); 667 668 rk_gpio_attach_ports(sc); 669 670 WR4(sc, GPIO_INTEN_REG, 0); 671 672 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 673 aprint_error_dev(self, "failed to decode interrupt\n"); 674 return; 675 } 676 sc->sc_ih = fdtbus_intr_establish_xname(phandle, 0, IPL_VM, 677 FDT_INTR_MPSAFE, rk_gpio_intr, sc, device_xname(self)); 678 if (sc->sc_ih == NULL) { 679 aprint_error_dev(self, "failed to establish interrupt on %s\n", 680 intrstr); 681 return; 682 } 683 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 684 fdtbus_register_interrupt_controller(self, phandle, 685 &rk_gpio_intrfuncs); 686 } 687
Indexes created Sat Sep 20 22:09:52 GMT 2025