| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/ |
| amdgpu_dcn21_hubp.c | 129 struct _vcs_dpi_display_rq_regs_st *rq_regs)
134 DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address);
136 DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode,
137 PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode,
138 MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode,
139 CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode);
141 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size,
142 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size,
143 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size,
144 MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size
362 struct _vcs_dpi_display_rq_regs_st rq_regs = {0}; local in function:hubp21_validate_dml_output
[all...] |
| dcn21_hubp.h | 135 struct _vcs_dpi_display_rq_regs_st *rq_regs);
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/ |
| amdgpu_display_rq_dlg_helpers.c | 164 void print__data_rq_regs_st(struct display_mode_lib *mode_lib, display_data_rq_regs_st rq_regs)
168 dml_print("DML_RQ_DLG_CALC: chunk_size = 0x%0x\n", rq_regs.chunk_size);
169 dml_print("DML_RQ_DLG_CALC: min_chunk_size = 0x%0x\n", rq_regs.min_chunk_size);
170 dml_print("DML_RQ_DLG_CALC: meta_chunk_size = 0x%0x\n", rq_regs.meta_chunk_size);
173 rq_regs.min_meta_chunk_size);
174 dml_print("DML_RQ_DLG_CALC: dpte_group_size = 0x%0x\n", rq_regs.dpte_group_size);
175 dml_print("DML_RQ_DLG_CALC: mpte_group_size = 0x%0x\n", rq_regs.mpte_group_size);
176 dml_print("DML_RQ_DLG_CALC: swath_height = 0x%0x\n", rq_regs.swath_height);
179 rq_regs.pte_row_height_linear);
183 void print__rq_regs_st(struct display_mode_lib *mode_lib, display_rq_regs_st rq_regs)
[all...] |
| dml1_display_rq_dlg_calc.h | 39 struct _vcs_dpi_display_rq_regs_st *rq_regs,
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| display_rq_dlg_helpers.h | 45 void print__rq_regs_st(struct display_mode_lib *mode_lib, display_rq_regs_st rq_regs);
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| display_mode_lib.h | 59 display_rq_regs_st *rq_regs,
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| amdgpu_dml1_display_rq_dlg_calc.c | 213 struct _vcs_dpi_display_data_rq_regs_st *rq_regs,
219 rq_regs->chunk_size = dml_log2(rq_sizing.chunk_bytes) - 10;
222 rq_regs->min_chunk_size = 0;
224 rq_regs->min_chunk_size = dml_log2(rq_sizing.min_chunk_bytes) - 8 + 1;
226 rq_regs->meta_chunk_size = dml_log2(rq_sizing.meta_chunk_bytes) - 10;
228 rq_regs->min_meta_chunk_size = 0;
230 rq_regs->min_meta_chunk_size = dml_log2(rq_sizing.min_meta_chunk_bytes) - 6 + 1;
232 rq_regs->dpte_group_size = dml_log2(rq_sizing.dpte_group_bytes) - 6;
233 rq_regs->mpte_group_size = dml_log2(rq_sizing.mpte_group_bytes) - 6;
238 struct _vcs_dpi_display_rq_regs_st *rq_regs,
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn20/ |
| display_rq_dlg_calc_20.h | 40 // and then populate the rq_regs struct
44 // rq_regs - struct that holds all the RQ registers field value.
48 display_rq_regs_st *rq_regs,
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| display_rq_dlg_calc_20v2.h | 40 // and then populate the rq_regs struct
44 // rq_regs - struct that holds all the RQ registers field value.
48 display_rq_regs_st *rq_regs,
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| amdgpu_display_rq_dlg_calc_20.c | 171 display_data_rq_regs_st *rq_regs,
177 rq_regs->chunk_size = dml_log2(rq_sizing.chunk_bytes) - 10;
180 rq_regs->min_chunk_size = 0;
182 rq_regs->min_chunk_size = dml_log2(rq_sizing.min_chunk_bytes) - 8 + 1;
184 rq_regs->meta_chunk_size = dml_log2(rq_sizing.meta_chunk_bytes) - 10;
186 rq_regs->min_meta_chunk_size = 0;
188 rq_regs->min_meta_chunk_size = dml_log2(rq_sizing.min_meta_chunk_bytes) - 6 + 1;
190 rq_regs->dpte_group_size = dml_log2(rq_sizing.dpte_group_bytes) - 6;
191 rq_regs->mpte_group_size = dml_log2(rq_sizing.mpte_group_bytes) - 6;
195 display_rq_regs_st *rq_regs,
[all...] |
| amdgpu_display_rq_dlg_calc_20v2.c | 171 display_data_rq_regs_st *rq_regs,
177 rq_regs->chunk_size = dml_log2(rq_sizing.chunk_bytes) - 10;
180 rq_regs->min_chunk_size = 0;
182 rq_regs->min_chunk_size = dml_log2(rq_sizing.min_chunk_bytes) - 8 + 1;
184 rq_regs->meta_chunk_size = dml_log2(rq_sizing.meta_chunk_bytes) - 10;
186 rq_regs->min_meta_chunk_size = 0;
188 rq_regs->min_meta_chunk_size = dml_log2(rq_sizing.min_meta_chunk_bytes) - 6 + 1;
190 rq_regs->dpte_group_size = dml_log2(rq_sizing.dpte_group_bytes) - 6;
191 rq_regs->mpte_group_size = dml_log2(rq_sizing.mpte_group_bytes) - 6;
195 display_rq_regs_st *rq_regs,
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn21/ |
| display_rq_dlg_calc_21.h | 40 // and then populate the rq_regs struct
44 // rq_regs - struct that holds all the RQ registers field value.
48 display_rq_regs_st *rq_regs,
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| amdgpu_display_rq_dlg_calc_21.c | 148 display_data_rq_regs_st *rq_regs,
154 rq_regs->chunk_size = dml_log2(rq_sizing.chunk_bytes) - 10;
157 rq_regs->min_chunk_size = 0;
159 rq_regs->min_chunk_size = dml_log2(rq_sizing.min_chunk_bytes) - 8 + 1;
161 rq_regs->meta_chunk_size = dml_log2(rq_sizing.meta_chunk_bytes) - 10;
163 rq_regs->min_meta_chunk_size = 0;
165 rq_regs->min_meta_chunk_size = dml_log2(rq_sizing.min_meta_chunk_bytes) - 6 + 1;
167 rq_regs->dpte_group_size = dml_log2(rq_sizing.dpte_group_bytes) - 6;
168 rq_regs->mpte_group_size = dml_log2(rq_sizing.mpte_group_bytes) - 6;
173 display_rq_regs_st *rq_regs,
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_hubp.c | 199 struct _vcs_dpi_display_rq_regs_st *rq_regs)
204 DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address);
206 DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode,
207 PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode,
208 MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode,
209 CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode);
211 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size,
212 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size,
213 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size,
214 MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size
1055 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; local in function:hubp2_read_state_common
1228 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; local in function:hubp2_read_state
1261 struct _vcs_dpi_display_rq_regs_st rq_regs = {0}; local in function:hubp2_validate_dml_output
[all...] |
| amdgpu_dcn20_hwseq.c | 1305 memcmp(&old_pipe->rq_regs, &new_pipe->rq_regs, sizeof(old_pipe->rq_regs)))
1335 &pipe_ctx->rq_regs,
1745 &pipe_ctx->rq_regs,
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| amdgpu_dcn20_resource.c | 2873 &context->res_ctx.pipe_ctx[i].rq_regs,
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_hubp.c | 547 struct _vcs_dpi_display_rq_regs_st *rq_regs)
552 DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address);
554 DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode,
555 PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode,
556 MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode,
557 CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode);
559 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size,
560 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size,
561 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size,
562 MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size
863 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; local in function:hubp1_read_state_common
1036 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; local in function:hubp1_read_state
[all...] |
| amdgpu_dcn10_hw_sequencer_debug.c | 210 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; local in function:dcn10_get_rq_states
217 pool->hubps[i]->inst, rq_regs->drq_expansion_mode, rq_regs->prq_expansion_mode, rq_regs->mrq_expansion_mode,
218 rq_regs->crq_expansion_mode, rq_regs->plane1_base_address, rq_regs->rq_regs_l.chunk_size,
219 rq_regs->rq_regs_l.min_chunk_size, rq_regs->rq_regs_l.meta_chunk_size
[all...] |
| amdgpu_dcn10_hw_sequencer.c | 201 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; local in function:dcn10_log_hubp_states
205 pool->hubps[i]->inst, rq_regs->drq_expansion_mode, rq_regs->prq_expansion_mode, rq_regs->mrq_expansion_mode,
206 rq_regs->crq_expansion_mode, rq_regs->plane1_base_address, rq_regs->rq_regs_l.chunk_size,
207 rq_regs->rq_regs_l.min_chunk_size, rq_regs->rq_regs_l.meta_chunk_size
[all...] |
| dcn10_hubp.h | 664 struct _vcs_dpi_display_rq_regs_st rq_regs; member in struct:dcn_hubp_state
708 struct _vcs_dpi_display_rq_regs_st *rq_regs);
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/ |
| hubp.h | 93 struct _vcs_dpi_display_rq_regs_st *rq_regs,
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| mem_input.h | 98 struct _vcs_dpi_display_rq_regs_st *rq_regs,
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/ |
| core_types.h | 299 struct _vcs_dpi_display_rq_regs_st rq_regs; member in struct:pipe_ctx
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/ |
| amdgpu_dcn_calcs.c | 452 struct _vcs_dpi_display_rq_regs_st *rq_regs = &pipe->rq_regs; local in function:dcn_bw_calc_rq_dlg_ttu
463 memset(rq_regs, 0, sizeof(*rq_regs));
497 dml1_extract_rq_regs(dml, rq_regs, rq_param);
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/ |
| amdgpu_dc.c | 2268 &context->res_ctx.pipe_ctx[i].rq_regs,
|
