| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/ |
| amdgpu_dcn21_hubp.c | 141 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size,
142 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size,
143 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size,
144 MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size,
145 DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size,
146 VM_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size,
147 SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height,
148 PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear);
377 CHUNK_SIZE, &rq_regs.rq_regs_l.chunk_size,
378 MIN_CHUNK_SIZE, &rq_regs.rq_regs_l.min_chunk_size
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_hubp.c | 211 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size,
212 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size,
213 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size,
214 MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size,
215 DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size,
216 MPTE_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size,
217 SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height,
218 PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear);
1233 CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size,
1234 MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_hw_sequencer_debug.c | 218 rq_regs->crq_expansion_mode, rq_regs->plane1_base_address, rq_regs->rq_regs_l.chunk_size,
219 rq_regs->rq_regs_l.min_chunk_size, rq_regs->rq_regs_l.meta_chunk_size,
220 rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs->rq_regs_l.dpte_group_size,
221 rq_regs->rq_regs_l.mpte_group_size, rq_regs->rq_regs_l.swath_height,
222 rq_regs->rq_regs_l.pte_row_height_linear, rq_regs->rq_regs_c.chunk_size, rq_regs->rq_regs_c.min_chunk_size,
|
| amdgpu_dcn10_hubp.c | 559 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size,
560 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size,
561 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size,
562 MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size,
563 DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size,
564 MPTE_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size,
565 SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height,
566 PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear);
1041 CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size,
1042 MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size
[all...] |
| amdgpu_dcn10_hw_sequencer.c | 206 rq_regs->crq_expansion_mode, rq_regs->plane1_base_address, rq_regs->rq_regs_l.chunk_size,
207 rq_regs->rq_regs_l.min_chunk_size, rq_regs->rq_regs_l.meta_chunk_size,
208 rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs->rq_regs_l.dpte_group_size,
209 rq_regs->rq_regs_l.mpte_group_size, rq_regs->rq_regs_l.swath_height,
210 rq_regs->rq_regs_l.pte_row_height_linear, rq_regs->rq_regs_c.chunk_size, rq_regs->rq_regs_c.min_chunk_size,
1801 pipe_ctx->rq_regs.rq_regs_l.chunk_size,
1802 pipe_ctx->rq_regs.rq_regs_l.min_chunk_size
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/ |
| amdgpu_display_rq_dlg_helpers.c | 188 print__data_rq_regs_st(mode_lib, rq_regs.rq_regs_l);
|
| display_mode_structs.h | 506 display_data_rq_regs_st rq_regs_l; member in struct:_vcs_dpi_display_rq_regs_st
|
| amdgpu_dml1_display_rq_dlg_calc.c | 244 extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), rq_param.sizing.rq_l);
248 rq_regs->rq_regs_l.swath_height = dml_log2(rq_param.dlg.rq_l.swath_height);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn20/ |
| amdgpu_display_rq_dlg_calc_20.c | 201 extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), rq_param.sizing.rq_l);
203 rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_l.dpte_row_height),
212 rq_regs->rq_regs_l.swath_height = dml_log2(rq_param.dlg.rq_l.swath_height);
|
| amdgpu_display_rq_dlg_calc_20v2.c | 201 extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), rq_param.sizing.rq_l);
203 rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_l.dpte_row_height),
212 rq_regs->rq_regs_l.swath_height = dml_log2(rq_param.dlg.rq_l.swath_height);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn21/ |
| amdgpu_display_rq_dlg_calc_21.c | 179 extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), rq_param.sizing.rq_l);
181 rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(
192 rq_regs->rq_regs_l.swath_height = dml_log2(rq_param.dlg.rq_l.swath_height);
|
