| /src/sys/arch/sparc/fpu/ |
| fpu.c | 305 int opf, rs1, rs2, rd, type, mask, fsr, cx; local in function:fpu_execute
308 int opf, rs1, rs2, rd, type, mask, fsr, cx, i, cond; local in function:fpu_execute
337 rs1 = instr.i_opf.i_rs1;
338 rs1 = (rs1 & ~mask) | ((rs1 & mask & 0x1) << 5);
344 if ((rs1 | rs2 | rd) & mask)
362 rs1 = fs->fs_regs[rs2];
368 rs1 = fs->fs_regs[rs2];
374 rs1 = fs->fs_regs[rs2]
[all...] |
| /src/sys/arch/sparc/sparc/ |
| emul.c | 134 union instr *code, int32_t *rd, int32_t *rs1, int32_t *rs2)
173 * ignore the error and return *rd = *rs1.
180 *rd = *rs1 / *rs2;
181 DPRINTF(("muldiv: %d / %d = %d\n", *rs1, *rs2, *rd));
184 *rd = *rs1 * *rs2;
185 DPRINTF(("muldiv: %d * %d = %d\n", *rs1, *rs2, *rd));
198 if (*rd * *rs2 != *rs1)
202 if (*rd / *rs2 != *rs1)
248 int32_t rs1, rs2; local in function:fixalign
274 if ((error = readgpreg(tf, code.i_op3.i_rs1, &rs1)) != 0)
388 int32_t rs1, rs2, rd; local in function:emulinstr
[all...] |
| /src/sys/arch/sparc64/sparc64/ |
| emul.c | 132 muldiv(struct trapframe64 *tf, union instr *code, int32_t *rd, int32_t *rs1,
172 * ignore the error and return *rd = *rs1.
179 *rd = *rs1 / *rs2;
180 DPRINTF(("muldiv: %d / %d = %d\n", *rs1, *rs2, *rd));
183 *rd = *rs1 * *rs2;
184 DPRINTF(("muldiv: %d * %d = %d\n", *rs1, *rs2, *rd));
197 if (*rd * *rs2 != *rs1)
201 if (*rd / *rs2 != *rs1)
245 int64_t rs1, rs2; local in function:fixalign
271 if ((error = readgpreg(tf, code.i_op3.i_rs1, &rs1)) != 0)
380 int32_t rs1, rs2, rd; local in function:emulinstr
[all...] |
| /src/sys/arch/sparc/include/ |
| instr.h | 220 * decode almost always makes use of an `rd' and `rs1', however
285 * `rs1' or `cond'.
349 #define _I_OP3_GEN(form, rd, op3, rs1, low14) \
350 _I_ANY(form, (rd) << 25 | (op3) << 19 | (rs1) << 14 | (low14))
351 #define _I_OP3_LS_RAR(rd, op3, rs1, asi, rs2) \
352 _I_OP3_GEN(IOP_mem, rd, op3, rs1, (asi) << 5 | (rs2))
353 #define _I_OP3_LS_RI(rd, op3, rs1, simm13) \
354 _I_OP3_GEN(IOP_mem, rd, op3, rs1, _I_SIMM(simm13))
355 #define _I_OP3_LS_RR(rd, op3, rs1, rs2) \
356 _I_OP3_GEN(IOP_mem, rd, op3, rs1, rs2
[all...] |
| /src/sys/arch/riscv/riscv/ |
| db_disasm.c | 140 unsigned rd, rs1, rs2; local in function:db_disasm_16
153 rs1 = INSN16_RS1x(insn);
158 riscv_registers[rs1]);
162 (int32_t)imm, riscv_registers[rs1]);
166 rs1 = INSN16_RS1x(insn);
170 (int32_t)imm, riscv_registers[rs1]);
173 rs1 = INSN16_RS1x(insn);
178 riscv_registers[rs1]);
182 (int32_t)imm, riscv_registers[rs1]);
186 rs1 = INSN16_RS1x(insn)
[all...] |
| db_machdep.c | 188 register_t rs1 = get_reg_value(tf, i.type_b.b_rs1); local in function:branch_taken
193 branch_p = (rs1 == rs2);
196 branch_p = ((rs1 & (1 << (i.type_b.b_rs2))) != 0);
199 branch_p = (rs1 < rs2);
203 branch_p = ((uregister_t)rs1 < (uregister_t)rs2);
|
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| xenvm-4.2.dts | 80 arm,v2m-memory-map = "rs1";
|
| vexpress-v2p-ca5s.dts | 12 #include "vexpress-v2m-rs1.dtsi"
|
| vexpress-v2p-ca15-tc1.dts | 12 #include "vexpress-v2m-rs1.dtsi"
|
| vexpress-v2m.dtsi | 14 * RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong
18 * CHANGES TO vexpress-v2m-rs1.dtsi!
|
| vexpress-v2p-ca15_a7.dts | 12 #include "vexpress-v2m-rs1.dtsi"
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/arm/ |
| vexpress-v2f-1xv7-ca53x2.dts | 16 #include "vexpress-v2m-rs1.dtsi"
|
| /src/sys/dev/ic/ |
| isp.c | 3349 sns_gid_ft_rsp_t *rs0, *rs1; local in function:isp_scan_fabric
3422 rs1 = (sns_gid_ft_rsp_t *) ((uint8_t *)fcp->isp_scratch+OGPOFF);
3423 isp_get_gid_ft_response(isp, rs0, rs1, NGENT);
3429 if (rs1->snscb_cthdr.ct_cmd_resp != LS_ACC) {
3431 if (rs1->snscb_cthdr.ct_reason == 9 &&
3432 rs1->snscb_cthdr.ct_explanation == 7) {
3439 rs1->snscb_cthdr.ct_reason,
3440 rs1->snscb_cthdr.ct_explanation);
3464 if (rs1->snscb_ports[portidx].control & 0x80) {
3472 if ((rs1->snscb_ports[portidx].control & 0x80) == 0)
[all...] |
| /src/share/terminfo/ |
| terminfo | 865 rs1=\E<\E[20l\E[?3;6;9l\E[r\Eq\E(B\017\E)0\E>,
890 rmso=\Eq, rmul=\EzH, rs1=\Ez_\Eb@\EcA, sgr0=\Ez_,
909 rmul=\EzH, rs1=\Ez_\Eb@\EcA, sgr0=\Ez_, smcup=\Ev\Ee\Ez_,
941 ri=\EI, rmcup=, rmso=\Eq, rs1=\Ez_\Eb@\EcA, sc=\Ej, sgr0=\Eq,
963 rmul=\E[24m, rs1=\Ec, sc=\E7, setab=\E[4%p1%dm,
1017 rmul=\E[24m, rs1=\Ec\E]R, sc=\E7,
1206 rmpch=\E[10m, rmso=\E[27m, rmul=\E[24m, rs1=\Ec, sc=\E7,
1389 rmso=\E[27m, rmul=\E[24m, rs1=\EM\E[?1000l, sc=\E7,
1460 rmso=\E), rmul=\E], rs1=\ER, setb=\E@%p1%Pb%gb%gf%d%d,
1535 rmul=\E[24m, rs1=\017\E[?7h\E[0;39;49m$<2>\E>\E[?1l
[all...] |
