| /src/sys/arch/sparc/fpu/ |
| fpu.c | 305 int opf, rs1, rs2, rd, type, mask, fsr, cx; local in function:fpu_execute
308 int opf, rs1, rs2, rd, type, mask, fsr, cx, i, cond; local in function:fpu_execute
339 rs2 = instr.i_opf.i_rs2;
340 rs2 = (rs2 & ~mask) | ((rs2 & mask & 0x1) << 5);
344 if ((rs1 | rs2 | rd) & mask)
362 rs1 = fs->fs_regs[rs2];
368 rs1 = fs->fs_regs[rs2];
374 rs1 = fs->fs_regs[rs2];
[all...] |
| /src/sys/arch/sparc/sparc/ |
| emul.c | 134 union instr *code, int32_t *rd, int32_t *rs1, int32_t *rs2)
164 uprintf("0x%x\n", *rs2);
170 if (*rs2 == 0) {
180 *rd = *rs1 / *rs2;
181 DPRINTF(("muldiv: %d / %d = %d\n", *rs1, *rs2, *rd));
184 *rd = *rs1 * *rs2;
185 DPRINTF(("muldiv: %d * %d = %d\n", *rs1, *rs2, *rd));
198 if (*rd * *rs2 != *rs1)
202 if (*rd / *rs2 != *rs1)
248 int32_t rs1, rs2; local in function:fixalign
388 int32_t rs1, rs2, rd; local in function:emulinstr
[all...] |
| /src/sys/arch/sparc64/sparc64/ |
| emul.c | 133 int32_t *rs2)
163 uprintf("0x%x\n", *rs2);
169 if (*rs2 == 0) {
179 *rd = *rs1 / *rs2;
180 DPRINTF(("muldiv: %d / %d = %d\n", *rs1, *rs2, *rd));
183 *rd = *rs1 * *rs2;
184 DPRINTF(("muldiv: %d * %d = %d\n", *rs1, *rs2, *rd));
197 if (*rd * *rs2 != *rs1)
201 if (*rd / *rs2 != *rs1)
245 int64_t rs1, rs2; local in function:fixalign
380 int32_t rs1, rs2, rd; local in function:emulinstr
[all...] |
| /src/sys/arch/sparc/include/ |
| instr.h | 225 * 1 bit of imm=0 + 8 bits of asi + 5 bits of rs2 [reg & mem]
227 * 9 bits of copressor `opf' opcode + 5 bits of rs2 [reg only]
289 * 1 bit of imm=0 + 8 bits of asi + 5 bits of rs2 [reg & mem]
291 * 9 bits of copressor `opf' opcode + 5 bits of rs2 [reg only] */
351 #define _I_OP3_LS_RAR(rd, op3, rs1, asi, rs2) \
352 _I_OP3_GEN(IOP_mem, rd, op3, rs1, (asi) << 5 | (rs2))
355 #define _I_OP3_LS_RR(rd, op3, rs1, rs2) \
356 _I_OP3_GEN(IOP_mem, rd, op3, rs1, rs2)
357 #define _I_OP3_R_RAR(rd, op3, rs1, asi, rs2) \
358 _I_OP3_GEN(IOP_reg, rd, op3, rs1, (asi) << 5 | (rs2))
[all...] |
| /src/sys/arch/riscv/riscv/ |
| db_disasm.c | 140 unsigned rd, rs1, rs2; local in function:db_disasm_16
187 rs2 = INSN16_RS2x(insn);
190 db_printf("c.fsd f%d, %d(%s)\n", rs2, (int32_t)imm,
194 db_printf("c.sq %s, %d(%s)\n", riscv_registers[rs2],
200 rs2 = INSN16_RS2x(insn);
202 db_printf("c.sw %s, %d(%s)\n", riscv_registers[rs2],
207 rs2 = INSN16_RS2x(insn);
210 db_printf("c.fsw f%d, %d(%s)\n", rs2, (int32_t)imm,
214 db_printf("c.sd %s, %d(%s)\n", riscv_registers[rs2],
300 rs2 = INSN16_RS2x(insn)
527 rs2: 5; member in struct:riscv_disasm_insn
[all...] |
| db_machdep.c | 189 register_t rs2 = get_reg_value(tf, i.type_b.b_rs2); local in function:branch_taken
193 branch_p = (rs1 == rs2);
199 branch_p = (rs1 < rs2);
203 branch_p = ((uregister_t)rs1 < (uregister_t)rs2);
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/arm/ |
| fvp-base-revc.dts | 18 #include "rtsm_ve-motherboard-rs2.dtsi"
|
| /src/share/terminfo/ |
| terminfo | 801 rmul=\EzH, rs2=\Ev\Eq\Ez_\Ee\Ei\Eb?\Ec0, sgr0=\Ez_,
808 is2=\Ev\Eq\Ee\Eb1\Ec0, rs2=\Ev\Eq\Ee\Eb1\Ec0,
843 rs2=\Ev\Eq\Ee, sc=\Ej, sgr0=\Eq, smso=\Ep,
1536 rs2=\E>\E[?3l\E[?4l\E[?5l\E[?7h\E[?8h,
1709 rs2=\E>\E[?3l\E[?4l\E[?5l\E[?7h\E[?8h,
1775 rmam=\E[?7l, rmul=\E[24m, rs2=\Ec, sc=\E7, smam=\E[?7h,
1901 rmul=\E[m$<2>, rs2=\E>\E[?3l\E[?4l\E[?5l\E[?7h\E[?8h,
2032 rev=\E[7m, ri=\E[T, rmso=\E[m, rs2=\E[x\E[m\Ec, sc=\E7,
2092 rs2=\E[x\E[m\Ec, sc=\E7, setab=\E[4%p1%dm,
2269 ri=\E[T, rmso=\E[27m, rs2=\E[x\E[m\Ec, setab=\E[4%p1%dm
[all...] |
