| /src/sys/dev/dtv/ |
| dtvvar.h | 111 const struct dtv_hw_if *sc_hw; member in struct:dtv_softc
131 ((sc)->sc_hw->get_devinfo((sc)->sc_priv, (info)))
133 ((sc)->sc_hw->open((sc)->sc_priv, (flags)))
135 ((sc)->sc_hw->close((sc)->sc_priv))
137 ((sc)->sc_hw->set_tuner((sc)->sc_priv, (params)))
139 ((sc)->sc_hw->get_status((sc)->sc_priv))
141 ((sc)->sc_hw->get_signal_strength((sc)->sc_priv))
143 ((sc)->sc_hw->get_snr((sc)->sc_priv))
145 ((sc)->sc_hw->start_transfer((sc)->sc_priv, dtv_buffer_submit, (sc)))
147 ((sc)->sc_hw->stop_transfer((sc)->sc_priv)
[all...] |
| dtv_device.c | 101 sc->sc_hw = daa->hw;
|
| /src/sys/arch/hppa/dev/ |
| lasi.c | 76 struct lasi_hwr volatile *sc_hw; member in struct:lasi_softc
173 sc->sc_hw = (struct lasi_hwr *)ioh;
177 aprint_normal(": rev %d.%d\n", (sc->sc_hw->lasi_version & 0xf0) >> 4,
178 sc->sc_hw->lasi_version & 0xf);
234 sc->sc_hw->lasi_power = LASI_BLINK;
237 sc->sc_hw->lasi_power = 0;
240 sc->sc_hw->lasi_power = LASI_OFF;
|
| asp.c | 130 volatile struct asp_hwr *sc_hw; member in struct:asp_softc
220 sc->sc_hw = (struct asp_hwr *)ioh;
240 /* sc->sc_hw->asp_reset = 1; */
258 asp_spus[sc->sc_trs->asp_spu].name, sc->sc_hw->asp_version,
|
| /src/sys/dev/pci/qat/ |
| qat.c | 423 memcpy(&sc->sc_hw, qatp->qatp_hw, sizeof(struct qat_hw));
426 sc->sc_accel_mask = sc->sc_hw.qhw_get_accel_mask(sc);
427 sc->sc_ae_mask = sc->sc_hw.qhw_get_ae_mask(sc);
430 for (i = 0; i < sc->sc_hw.qhw_num_accel; i++) {
435 for (i = 0; i < sc->sc_hw.qhw_num_engines; i++) {
450 sc->sc_sku = sc->sc_hw.qhw_get_sku(sc);
451 sc->sc_accel_cap = sc->sc_hw.qhw_get_accel_cap(sc);
452 sc->sc_fw_uof_name = sc->sc_hw.qhw_get_fw_uof_name(sc);
475 if (sc->sc_hw.qhw_sram_bar_id != NO_PCI_REG) {
476 KASSERT(sc->sc_hw.qhw_sram_bar_id == 0)
[all...] |
| qatvar.h | 824 struct qat_hw sc_hw; member in struct:qat_softc
961 qat_bar_write_4(sc, sc->sc_hw.qhw_misc_bar_id, offset, value);
968 return qat_bar_read_4(sc, sc->sc_hw.qhw_misc_bar_id, offset);
997 qat_bar_write_4(sc, sc->sc_hw.qhw_etr_bar_id, offset, value);
1004 return qat_bar_read_4(sc, sc->sc_hw.qhw_etr_bar_id, offset);
1015 qat_misc_write_4(sc, sc->sc_hw.qhw_ae_local_offset + offset,
1026 return qat_misc_read_4(sc, sc->sc_hw.qhw_ae_local_offset + offset);
1036 qat_misc_write_4(sc, sc->sc_hw.qhw_ae_offset + offset, value);
1043 qat_misc_write_4(sc, sc->sc_hw.qhw_cap_global_offset + offset, value);
1050 return qat_misc_read_4(sc, sc->sc_hw.qhw_cap_global_offset + offset)
[all...] |
| qat_hw17.c | 223 sc->sc_hw.qhw_clock_per_sec / 1000 * QAT_HB_INTERVAL;
300 sc->sc_hw.qhw_get_arb_mapping(sc, &thd_2_arb_cfg);
305 for (i = 0; i < sc->sc_hw.qhw_num_engines; i++)
318 timer = sc->sc_hw.qhw_clock_per_sec / 1000 * QAT_SSM_WDT;
|
| qat_hw15.c | 229 ADMIN_RING_SIZE, sc->sc_hw.qhw_fw_req_size,
235 ADMIN_RING_SIZE, sc->sc_hw.qhw_fw_resp_size,
321 param = &tbl->firt_bulk_rings[sc->sc_hw.qhw_ring_sym_tx];
324 FW_INIT_RING_MASK_SET(tbl, sc->sc_hw.qhw_ring_sym_tx);
|
| qat_ae.c | 982 if (!sc->sc_hw.qhw_fw_auth) {
1866 error = firmware_open("qat", sc->sc_hw.qhw_mof_fwname, &fh);
1869 sc->sc_hw.qhw_mof_fwname);
1904 error = firmware_open("qat", sc->sc_hw.qhw_mmp_fwname, &fh);
1907 sc->sc_hw.qhw_mmp_fwname);
2328 if ((uoh->uoh_cpu_type & sc->sc_hw.qhw_prod_type) == 0)
2404 if (ae_mode->sam_dev_type != sc->sc_hw.qhw_prod_type)
2855 if (sc->sc_hw.qhw_fw_auth) {
2902 if (sc->sc_hw.qhw_fw_auth) {
|
| /src/sys/dev/spi/ |
| spiflash.c | 77 struct spiflash_hw_if sc_hw; member in struct:spiflash_softc
94 #define sc_getname sc_hw.sf_getname
95 #define sc_gethandle sc_hw.sf_gethandle
96 #define sc_getsize sc_hw.sf_getsize
97 #define sc_getflags sc_hw.sf_getflags
98 #define sc_erase sc_hw.sf_erase
99 #define sc_write sc_hw.sf_write
100 #define sc_read sc_hw.sf_read
101 #define sc_getstatus sc_hw.sf_getstatus
102 #define sc_setstatus sc_hw.sf_setstatu
[all...] |
