| /src/sys/arch/hppa/dev/ |
| elroyvar.h | 35 uint32_t sc_imr; member in struct:elroy_softc
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| apic.c | 210 sc->sc_imr |= (1 << irq);
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| /src/sys/arch/vax/uba/ |
| qvavar.h | 107 int sc_imr; /* interrupts that are enabled */ member in struct:qvaux_softc
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| qvaux.c | 362 sc->sc_imr = INT_RXA | INT_RXB;
363 qvaux_write2(sc, sc->sc_qr.qr_imr, sc->sc_imr);
387 if (isr & (INT_TXA | INT_TXB) & sc->sc_imr)
470 || ((sc->sc_imr & INT_TXA) == 0)) {
472 || ((sc->sc_imr & INT_TXB) == 0))
493 sc->sc_imr &= ~((line) ? (INT_TXB) : (INT_TXA));
494 qvaux_write2(sc, sc->sc_qr.qr_imr, sc->sc_imr);
712 sc->sc_imr |= ((line) ? (INT_TXB) : (INT_TXA));
713 qvaux_write2(sc, sc->sc_qr.qr_imr, sc->sc_imr);
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| /src/sys/dev/ic/ |
| dp83932var.h | 200 uint16_t sc_imr; /* prototype IMR */ member in struct:sonic_softc
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| dp83932.c | 582 isr = CSR_READ(sc, SONIC_ISR) & sc->sc_imr;
1015 sc->sc_imr = IMR_RFO | IMR_RBA | IMR_RBE | IMR_RDE |
1017 CSR_WRITE(sc, SONIC_IMR, sc->sc_imr);
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| /src/sys/dev/pci/ |
| if_sip.c | 269 uint32_t sc_imr; /* prototype IMR register */ member in struct:sip_softc
1912 if ((isr & sc->sc_imr) == 0)
1982 if (sc->sc_imr & (ISR_PAUSE_END | ISR_PAUSE_ST)) {
2782 sc->sc_imr = sc->sc_bits.b_isr_dperr |
2788 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr);
3640 sc->sc_imr |= (ISR_PAUSE_END | ISR_PAUSE_ST);
3643 sc->sc_imr &= ~(ISR_PAUSE_END | ISR_PAUSE_ST);
3651 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr);
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| /src/sys/arch/arm/xilinx/ |
| zynq_uart.c | 1093 if (ISSET(sc->sc_imr, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC))
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