| /src/sys/arch/mips/atheros/dev/ |
| if_ae.c | 666 sc->sc_txdescs[nexttx].ad_status =
668 sc->sc_txdescs[nexttx].ad_bufaddr1 =
670 sc->sc_txdescs[nexttx].ad_ctl =
681 sc->sc_txdescs[sc->sc_txnext].ad_ctl |= ADCTL_Tx_FS;
682 sc->sc_txdescs[lasttx].ad_ctl |= ADCTL_Tx_LS;
690 sc->sc_txdescs[seg].ad_status);
692 sc->sc_txdescs[seg].ad_ctl);
694 sc->sc_txdescs[seg].ad_bufaddr1);
696 sc->sc_txdescs[seg].ad_bufaddr2);
737 sc->sc_txdescs[lasttx].ad_ctl |= ADCTL_Tx_IC
[all...] |
| aevar.h | 171 #define sc_txdescs sc_control_data->acd_txdescs macro
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| /src/sys/dev/ic/ |
| elinkxlvar.h | 56 struct ex_txdesc sc_txdescs[EX_NDPD]; member in struct:ex_softc
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| aic6915var.h | 139 #define sc_txdescs sc_control_data->scd_txdescs macro
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| atw.c | 1265 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs));
1267 sc->sc_txdescs[i].at_ctl = 0;
1269 sc->sc_txdescs[i].at_flags = 0 /* ATW_TXFLAG_TCH */;
1270 sc->sc_txdescs[i].at_buf2 =
1274 sc->sc_txdescs[ATW_NTXDESC - 1].at_flags |= htole32(ATW_TXFLAG_TER);
3304 le32toh(sc->sc_txdescs[i].at_stat));
3306 le32toh(sc->sc_txdescs[i].at_flags));
3308 le32toh(sc->sc_txdescs[i].at_buf1));
3310 le32toh(sc->sc_txdescs[i].at_buf2))
[all...] |
| gem.c | 951 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs));
953 sc->sc_txdescs[i].gd_flags = 0;
954 sc->sc_txdescs[i].gd_addr = 0;
1354 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_flags));
1356 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr));
1539 sc->sc_txdescs[nexttx].gd_addr =
1545 sc->sc_txdescs[nexttx].gd_flags =
1553 sc->sc_txdescs[lasttx].gd_flags =
1556 sc->sc_txdescs[nexttx].gd_addr
[all...] |
| gemvar.h | 193 #define sc_txdescs sc_control_data->gcd_txdescs macro
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| aic6915.c | 388 txd = &sc->sc_txdescs[producer];
479 sc->sc_txdescs[last].td_word0 |= TD_W0_INTR;
940 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs));
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| elinkxl.c | 1644 sc->sc_txdescs[i].tx_dmamap = sc->sc_tx_dmamaps[i];
1645 sc->sc_txdescs[i].tx_dpd = &sc->sc_dpd[i];
1647 sc->sc_txdescs[i].tx_next = &sc->sc_txdescs[i + 1];
1649 sc->sc_txdescs[i].tx_next = NULL;
1651 sc->tx_free = &sc->sc_txdescs[0];
1652 sc->tx_ftail = &sc->sc_txdescs[EX_NDPD-1];
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| atwvar.h | 222 #define sc_txdescs sc_control_data->acd_txdescs macro
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| tulip.c | 808 txd = &sc->sc_txdescs[nexttx];
824 sc->sc_txdescs[sc->sc_txnext].td_ctl |= htole32(TDCTL_Tx_FS);
825 sc->sc_txdescs[lasttx].td_ctl |= htole32(TDCTL_Tx_LS);
831 txd = &sc->sc_txdescs[seg];
883 sc->sc_txdescs[lasttx].td_ctl |= htole32(TDCTL_Tx_IC);
894 sc->sc_txdescs[last_txs->txs_firstdesc].td_ctl |=
904 sc->sc_txdescs[firsttx].td_status |= htole32(TDSTAT_OWN);
1424 txd = &sc->sc_txdescs[i];
1433 le32toh(sc->sc_txdescs[i].td_bufaddr2));
1440 txstat = le32toh(sc->sc_txdescs[txs->txs_lastdesc].td_status)
[all...] |
| tulipvar.h | 426 #define sc_txdescs sc_control_data->tcd_txdescs macro
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| /src/sys/dev/pci/ |
| if_pcn.c | 263 #define sc_txdescs sc_control_data->pcd_txdescs macro
1047 sc->sc_txdescs[nexttx].tmd0 = 0;
1048 sc->sc_txdescs[nexttx].tmd2 =
1050 sc->sc_txdescs[nexttx].tmd1 =
1067 sc->sc_txdescs[nexttx].tmd0 =
1069 sc->sc_txdescs[nexttx].tmd2 = 0;
1070 sc->sc_txdescs[nexttx].tmd1 =
1082 sc->sc_txdescs[lasttx].tmd1 |= htole32(LE_T1_LTINT);
1085 sc->sc_txdescs[lasttx].tmd1 |= htole32(LE_T1_ENP);
1086 sc->sc_txdescs[sc->sc_txnext].tmd1 |
[all...] |
| if_ste.c | 144 #define sc_txdescs sc_control_data->scd_txdescs macro
686 tfd = &sc->sc_txdescs[nexttx];
792 sc->sc_txdescs[sc->sc_txlast].tfd_next = 0;
793 sc->sc_txdescs[sc->sc_txlast].tfd_control |=
802 sc->sc_txdescs[olasttx].tfd_next =
1004 control = le32toh(sc->sc_txdescs[i].tfd_control);
1243 control = le32toh(sc->sc_txdescs[id].tfd_control);
1245 sc->sc_txdescs[id].tfd_control = htole32(control);
1285 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs));
[all...] |
| if_casvar.h | 195 #define sc_txdescs sc_control_data->ccd_txdescs macro
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| if_kse.c | 247 #define sc_txdescs sc_control_data->kcd_txdescs macro
723 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs));
725 sc->sc_txdescs[i].t3 = paddr;
728 sc->sc_txdescs[KSE_NTXDESC - 1].t3 = KSE_CDTXADDR(sc, 0);
989 struct tdes *tdes = &sc->sc_txdescs[nexttx];
1014 sc->sc_txdescs[lasttx].t1 |= T1_IC;
1020 sc->sc_txdescs[lasttx].t1 |= T1_LS;
1021 sc->sc_txdescs[sc->sc_txnext].t1 |= T1_FS;
1022 sc->sc_txdescs[sc->sc_txnext].t0 = T0_OWN
[all...] |
| if_dge.c | 281 #define sc_txdescs sc_control_data->wcd_txdescs macro
1154 t = (struct dge_ctdes *)&sc->sc_txdescs[sc->sc_txnext];
1333 sc->sc_txdescs[nexttx].dt_baddrh =
1335 sc->sc_txdescs[nexttx].dt_baddrl =
1337 sc->sc_txdescs[nexttx].dt_ctl =
1339 sc->sc_txdescs[nexttx].dt_status = 0;
1340 sc->sc_txdescs[nexttx].dt_popts = cksumfields;
1341 sc->sc_txdescs[nexttx].dt_vlan = 0;
1359 sc->sc_txdescs[lasttx].dt_ctl |=
1366 lasttx, le32toh(sc->sc_txdescs[lasttx].dt_ctl)))
[all...] |
| if_vge.c | 216 #define sc_txdescs sc_control_data->vcd_txdescs macro
1376 txstat = le32toh(sc->sc_txdescs[idx].td_sts);
1524 txd = &sc->sc_txdescs[idx];
1689 sc->sc_txdescs[pidx].td_frag[0].tf_buflen |=
1763 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs));
1765 VGE_CDTXOFF(0), sizeof(sc->sc_txdescs),
|
| if_stge.c | 157 #define sc_txdescs sc_control_data->scd_txdescs macro
863 tfd = &sc->sc_txdescs[nexttx];
1193 control = le64toh(sc->sc_txdescs[i].tfd_control);
1519 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs));
1521 sc->sc_txdescs[i].tfd_next = htole64(
1523 sc->sc_txdescs[i].tfd_control = htole64(TFD_TFDDone);
|
| if_sip.c | 243 #define sc_txdescs sc_control_data->scd_txdescs macro
536 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs));
538 sipd = &sc->sc_txdescs[i];
560 struct sip_desc *sipd = &sc->sc_txdescs[x];
1497 sc->sc_txdescs[lasttx].sipd_words[sc->sc_extsts_idx] |=
1527 sc->sc_txdescs[sc->sc_txnext].sipd_words[sc->sc_extsts_idx] |= extsts;
1689 sc->sc_txdescs[lasttx].sipd_words[sc->sc_cmdsts_idx] |=
1705 sc->sc_txdescs[sc->sc_txnext].sipd_words[sc->sc_cmdsts_idx] |=
2052 cmdsts = le32toh(sc->sc_txdescs[
[all...] |
| if_cas.c | 1083 sc->sc_txdescs[i].cd_flags = 0;
1084 sc->sc_txdescs[i].cd_addr = 0;
2086 sc->sc_txdescs[frag].cd_addr =
2091 sc->sc_txdescs[frag].cd_flags = CAS_DMA_WRITE(flags);
|
| /src/sys/arch/evbppc/virtex/dev/ |
| if_temac.c | 170 #define sc_txdescs sc_control_data->cd_txdesc macro
416 sc->sc_txdescs[i].desc_next = sc->sc_cdaddr +
418 sc->sc_txdescs[i].desc_stat = CDMAC_STAT_DONE;
423 sc->sc_txdescs[i].desc_stat = CDMAC_STAT_DONE;
742 sc->sc_txdescs[sc->sc_txcur].desc_addr =
744 sc->sc_txdescs[sc->sc_txcur].desc_size =
746 sc->sc_txdescs[sc->sc_txcur].desc_stat =
768 sc->sc_txdescs[tail].desc_stat |= CDMAC_STAT_STOP |
|
| /src/sys/arch/powerpc/ibm4xx/dev/ |
| if_emac.c | 189 #define sc_txdescs sc_control_data->ecd_txdesc macro
769 &sc->sc_txdescs[nexttx];
787 sc->sc_txdescs[lasttx].md_stat_ctrl |= MAL_TX_LAST;
794 sc->sc_txdescs[lasttx].md_stat_ctrl |= MAL_TX_INTERRUPT;
807 sc->sc_txdescs[firsttx].md_stat_ctrl |= MAL_TX_READY;
903 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs));
905 sc->sc_txdescs[EMAC_NTXDESC - 1].md_stat_ctrl |= MAL_TX_WRAP;
1273 txstat = sc->sc_txdescs[txs->txs_lastdesc].md_stat_ctrl;
|
| /src/sys/arch/arm/sociox/ |
| if_scx.c | 480 #define sc_txdescs sc_control_data->cd_txdescs macro
1138 memset(sc->sc_txdescs, 0, sizeof(struct tdes) * MD_NTXDESC);
1139 sc->sc_txdescs[MD_NTXDESC - 1].t0 = htole32(T0_LD); /* tie off */
1431 struct tdes *tdes = &sc->sc_txdescs[nexttx];
1455 sc->sc_txdescs[lasttx].t0 |= htole32(T0_LS);
1456 sc->sc_txdescs[sc->sc_txnext].t0 |= htole32(T0_FS | T0_OWN);
1578 txstat = le32toh(sc->sc_txdescs[txs->txs_lastdesc].t0);
|
