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    Searched refs:scale_ratio_depth (Results 1 - 8 of 8) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/
amdgpu_dcn_calcs.c 390 input->scale_ratio_depth.hscl_ratio = pipe->plane_res.scl_data.ratios.horz.value/4294967296.0;
391 input->scale_ratio_depth.vscl_ratio = pipe->plane_res.scl_data.ratios.vert.value/4294967296.0;
392 input->scale_ratio_depth.vinit = pipe->plane_res.scl_data.inits.v.value/4294967296.0;
393 if (input->scale_ratio_depth.vinit < 1.0)
394 input->scale_ratio_depth.vinit = 1;
398 input->scale_ratio_depth.hscl_ratio_c = pipe->plane_res.scl_data.ratios.horz_c.value/4294967296.0;
399 input->scale_ratio_depth.vscl_ratio_c = pipe->plane_res.scl_data.ratios.vert_c.value/4294967296.0;
400 input->scale_ratio_depth.vinit_c = pipe->plane_res.scl_data.inits.v_c.value/4294967296.0;
401 if (input->scale_ratio_depth.vinit_c < 1.0)
402 input->scale_ratio_depth.vinit_c = 1
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/
amdgpu_dml1_display_rq_dlg_calc.c 1206 hratios_l = e2e_pipe_param.pipe.scale_ratio_depth.hscl_ratio;
1207 hratios_c = e2e_pipe_param.pipe.scale_ratio_depth.hscl_ratio_c;
1208 vratio_l = e2e_pipe_param.pipe.scale_ratio_depth.vscl_ratio;
1209 vratio_c = e2e_pipe_param.pipe.scale_ratio_depth.vscl_ratio_c;
1212 vinit_l = e2e_pipe_param.pipe.scale_ratio_depth.vinit;
1213 vinit_c = e2e_pipe_param.pipe.scale_ratio_depth.vinit_c;
1214 vinit_bot_l = e2e_pipe_param.pipe.scale_ratio_depth.vinit_bot;
1215 vinit_bot_c = e2e_pipe_param.pipe.scale_ratio_depth.vinit_bot_c;
1814 hratios_cur0 = e2e_pipe_param.pipe.scale_ratio_depth.hscl_ratio;
display_mode_structs.h 343 scaler_ratio_depth_st scale_ratio_depth; member in struct:_vcs_dpi_display_pipe_params_st
amdgpu_display_mode_vba.c 376 scaler_ratio_depth_st *scl = &pipes[j].pipe.scale_ratio_depth;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn21/
amdgpu_display_rq_dlg_calc_21.c 715 full_src_vp_width = pipe_param.scale_ratio_depth.hscl_ratio_c * pipe_param.dest.full_recout_width;
716 src_hactive_half = pipe_param.scale_ratio_depth.hscl_ratio_c * hactive_half;
718 full_src_vp_width = pipe_param.scale_ratio_depth.hscl_ratio * pipe_param.dest.full_recout_width;
719 src_hactive_half = pipe_param.scale_ratio_depth.hscl_ratio * hactive_half;
832 const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_resource.c 2089 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16;
2090 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = 1.0;
2091 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = 1.0;
2092 pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable = 0; /*Lb only or Full scl*/
2146 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16;
2147 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = (double) scl->ratios.horz.value / (1ULL<<32);
2148 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio_c = (double) scl->ratios.horz_c.value / (1ULL<<32);
2149 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = (double) scl->ratios.vert.value / (1ULL<<32);
2150 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio_c = (double) scl->ratios.vert_c.value / (1ULL<<32);
2151 pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn20/
amdgpu_display_rq_dlg_calc_20.c 786 const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth;
amdgpu_display_rq_dlg_calc_20v2.c 786 const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth;

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