| /src/sys/external/bsd/gnu-efi/dist/lib/ia32/ |
| setjmp.S | 22 .def setjmp; .scl 2; .type 32; .endef
39 .def longjmp; .scl 2; .type 32; .endef
|
| /src/sys/external/bsd/gnu-efi/dist/lib/x86_64/ |
| setjmp.S | 8 .def setjmp; .scl 2; .type 32; .endef
28 .def longjmp; .scl 2; .type 32; .endef
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| amdgpu_dce_hwseq.c | 57 uint32_t dcp_grph, scl, blnd, update_lock_mode, val; local
67 BLND_SCL_V_UPDATE_LOCK, &scl,
72 scl = lock_val;
78 BLND_SCL_V_UPDATE_LOCK, scl);
|
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/st/ |
| stm32h743i-eval.dts | 107 i2c-scl-rising-time-ns = <185>;
108 i2c-scl-falling-time-ns = <20>;
|
| stm32746g-eval.dts | 156 i2c-scl-rising-time-ns = <185>;
157 i2c-scl-falling-time-ns = <20>;
|
| stm32f746-disco.dts | 130 i2c-scl-rising-time-ns = <185>;
131 i2c-scl-falling-time-ns = <20>;
|
| stm32f769-disco.dts | 172 i2c-scl-rising-time-ns = <185>;
173 i2c-scl-falling-time-ns = <20>;
|
| stm32mp15xx-osd32.dtsi | 60 i2c-scl-rising-time-ns = <185>;
61 i2c-scl-falling-time-ns = <20>;
|
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/allwinner/ |
| sun5i-a13-utoo-p66.dts | 65 scl-gpios = <&pio 6 10 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG10 */
|
| sun6i-a31-colombus.dts | 67 scl-gpios = <&pio 0 24 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PA24 */
|
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/ |
| amdgpu_vega10_processpptables.c | 384 static void get_scl_sda_value(uint8_t line, uint8_t *scl, uint8_t* sda)
388 *scl = Vega10_I2C_DDC1CLK;
392 *scl = Vega10_I2C_DDC2CLK;
396 *scl = Vega10_I2C_DDC3CLK;
400 *scl = Vega10_I2C_DDC4CLK;
404 *scl = Vega10_I2C_DDC5CLK;
408 *scl = Vega10_I2C_DDC6CLK;
412 *scl = Vega10_I2C_SCL;
416 *scl = Vega10_I2C_DDCVGACLK;
420 *scl = 0
433 uint8_t scl; local
[all...] |
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/nxp/mxs/ |
| imx23-sansa.dts | 179 scl-gpios = <&gpio1 22 0>;
188 scl-gpios = <&gpio0 30 0>;
|
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/nxp/imx/ |
| imx6q-bx50v3.dtsi | 177 scl-gpios = <&gpio5 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
321 scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
328 scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
| imx6qdl-ts4900.dtsi | 129 scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
152 scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>;
|
| imx53-tx53-x13x.dts | 127 scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
|
| imx6qdl-ts7970.dtsi | 211 scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
250 scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>;
|
| /src/usr.bin/xlint/lint1/ |
| decl.c | 1602 new_tag(sym_t *tag, scl_t scl, bool decl, bool semi)
1612 warning(44, tag_name(scl),
1615 } else if (tag->s_scl != scl)
1626 } else if (tag->s_scl != scl) {
1632 warning(44, tag_name(scl), tag->s_name);
1637 if (tag->s_scl != scl ||
1641 tag->s_name, tag_name(scl));
1663 scl_t scl; local
1667 scl = STRUCT_TAG;
1669 scl = UNION_TAG
3147 scl_t scl = sym->s_scl; local
[all...] |
| /src/sys/dev/ |
| fss.c | 992 struct fss_cache *scp, *scl; local
997 scl = sc->sc_cache+sc->sc_cache_size;
1007 for (scp = sc->sc_cache; scp < scl; scp++) {
1021 for (scp = sc->sc_cache; scp < scl; scp++)
1027 if (scp >= scl) {
1166 struct fss_cache *scp, *scl; local
1169 scl = sc->sc_cache+sc->sc_cache_size;
1338 for (scp = sc->sc_cache; scp < scl; scp++)
1342 if (scp < scl)
|
| /src/sys/external/bsd/compiler_rt/dist/lib/builtins/ |
| assembly.h | 52 .scl 2 SEPARATOR \
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn20/ |
| amdgpu_display_rq_dlg_calc_20.c | 786 const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth; local
978 hratio_l = scl->hscl_ratio;
979 hratio_c = scl->hscl_ratio_c;
980 vratio_l = scl->vscl_ratio;
981 vratio_c = scl->vscl_ratio_c;
982 scl_enable = scl->scl_enable;
985 // vinit_l = scl.vinit;
986 // vinit_c = scl.vinit_c;
987 // vinit_bot_l = scl.vinit_bot;
988 // vinit_bot_c = scl.vinit_bot_c
[all...] |
| amdgpu_display_rq_dlg_calc_20v2.c | 786 const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth; local
979 hratio_l = scl->hscl_ratio;
980 hratio_c = scl->hscl_ratio_c;
981 vratio_l = scl->vscl_ratio;
982 vratio_c = scl->vscl_ratio_c;
983 scl_enable = scl->scl_enable;
986 // vinit_l = scl.vinit;
987 // vinit_c = scl.vinit_c;
988 // vinit_bot_l = scl.vinit_bot;
989 // vinit_bot_c = scl.vinit_bot_c
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn21/ |
| amdgpu_display_rq_dlg_calc_21.c | 832 const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth; local
1030 hratio_l = scl->hscl_ratio;
1031 hratio_c = scl->hscl_ratio_c;
1032 vratio_l = scl->vscl_ratio;
1033 vratio_c = scl->vscl_ratio_c;
1034 scl_enable = scl->scl_enable;
1450 scl->hscl_ratio,
1467 scl->hscl_ratio,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_resource.c | 2092 pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable = 0; /*Lb only or Full scl*/
2101 struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data; local
2110 pipes[pipe_cnt].pipe.src.viewport_y_y = scl->viewport.y;
2111 pipes[pipe_cnt].pipe.src.viewport_y_c = scl->viewport_c.y;
2112 pipes[pipe_cnt].pipe.src.viewport_width = scl->viewport.width;
2113 pipes[pipe_cnt].pipe.src.viewport_width_c = scl->viewport_c.width;
2114 pipes[pipe_cnt].pipe.src.viewport_height = scl->viewport.height;
2115 pipes[pipe_cnt].pipe.src.viewport_height_c = scl->viewport_c.height;
2130 pipes[pipe_cnt].pipe.dest.recout_width = scl->recout.width;
2131 pipes[pipe_cnt].pipe.dest.recout_height = scl->recout.height
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/ |
| amdgpu_display_mode_vba.c | 376 scaler_ratio_depth_st *scl = &pipes[j].pipe.scale_ratio_depth; local
411 mode_lib->vba.HRatio[mode_lib->vba.NumberOfActivePlanes] = scl->hscl_ratio;
412 mode_lib->vba.HRatioChroma[mode_lib->vba.NumberOfActivePlanes] = scl->hscl_ratio_c;
413 mode_lib->vba.VRatio[mode_lib->vba.NumberOfActivePlanes] = scl->vscl_ratio;
414 mode_lib->vba.VRatioChroma[mode_lib->vba.NumberOfActivePlanes] = scl->vscl_ratio_c;
415 mode_lib->vba.ScalerEnabled[mode_lib->vba.NumberOfActivePlanes] = scl->scl_enable;
526 switch (scl->lb_depth) {
|
| /src/sys/dev/pci/ |
| igma.c | 563 int sda, scl; local
568 scl = reg & GPIO_CLOCK_VAL_IN;
570 reg = (sda ? 1 : 0) | (scl ? 2 : 0);
|
