| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_dpp_dscl.c | 303 const struct scaler_data *scl_data,
310 uint32_t h_2tap_sharp_factor = scl_data->sharpness.horz;
311 uint32_t v_2tap_sharp_factor = scl_data->sharpness.vert;
318 h_2tap_hardcode_coef_en = scl_data->taps.h_taps < 3
319 && scl_data->taps.h_taps_c < 3
320 && (scl_data->taps.h_taps > 1 && scl_data->taps.h_taps_c > 1);
321 v_2tap_hardcode_coef_en = scl_data->taps.v_taps < 3
322 && scl_data->taps.v_taps_c < 3
323 && (scl_data->taps.v_taps > 1 && scl_data->taps.v_taps_c > 1)
[all...] |
| amdgpu_dcn10_dpp.c | 139 struct scaler_data *scl_data,
144 if (scl_data->viewport.width > scl_data->recout.width)
145 pixel_width = scl_data->recout.width;
147 pixel_width = scl_data->viewport.width;
150 if (scl_data->format == PIXEL_FORMAT_FP16 &&
152 scl_data->ratios.horz.value != dc_fixpt_one.value &&
153 scl_data->ratios.vert.value != dc_fixpt_one.value)
156 if (scl_data->viewport.width > scl_data->h_active &
[all...] |
| amdgpu_dcn10_hw_sequencer.c | 1946 pipe_ctx->plane_res.scl_data.viewport.width,
1947 pipe_ctx->plane_res.scl_data.viewport.height,
1948 pipe_ctx->plane_res.scl_data.viewport.x,
1949 pipe_ctx->plane_res.scl_data.viewport.y,
1950 pipe_ctx->plane_res.scl_data.recout.width,
1951 pipe_ctx->plane_res.scl_data.recout.height,
1952 pipe_ctx->plane_res.scl_data.recout.x,
1953 pipe_ctx->plane_res.scl_data.recout.y);
2051 switch (pipe_ctx->plane_res.scl_data.format) {
2093 switch (top_pipe_ctx->plane_res.scl_data.format)
[all...] |
| dcn10_dpp.h | 1361 struct scaler_data scl_data; member in struct:dcn10_dpp
1392 const struct scaler_data *scl_data,
1484 const struct scaler_data *scl_data);
1507 struct scaler_data *scl_data,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_dpp.c | 270 const struct scaler_data *scl_data,
278 int line_size = scl_data->viewport.width < scl_data->recout.width ?
279 scl_data->viewport.width : scl_data->recout.width;
280 int line_size_c = scl_data->viewport_c.width < scl_data->recout.width ?
281 scl_data->viewport_c.width : scl_data->recout.width;
315 if (scl_data->lb_params.alpha_e
[all...] |
| amdgpu_dcn20_hwseq.c | 1068 pipe_ctx->plane_res.scl_data.viewport.width,
1069 pipe_ctx->plane_res.scl_data.viewport.height,
1070 pipe_ctx->plane_res.scl_data.viewport.x,
1071 pipe_ctx->plane_res.scl_data.viewport.y,
1072 pipe_ctx->plane_res.scl_data.recout.width,
1073 pipe_ctx->plane_res.scl_data.recout.height,
1074 pipe_ctx->plane_res.scl_data.recout.x,
1075 pipe_ctx->plane_res.scl_data.recout.y);
1248 if (memcmp(&old_pipe->plane_res.scl_data, &new_pipe->plane_res.scl_data, sizeof(struct scaler_data))
[all...] |
| amdgpu_dcn20_resource.c | 1753 struct scaler_data *sd = &prev_odm_pipe->plane_res.scl_data;
1770 sd = &next_odm_pipe->plane_res.scl_data;
2101 struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data;
2136 res_ctx->pipe_ctx[i].bottom_pipe->plane_res.scl_data.recout.width;
2138 res_ctx->pipe_ctx[i].bottom_pipe->plane_res.scl_data.recout.height;
2141 res_ctx->pipe_ctx[i].top_pipe->plane_res.scl_data.recout.width;
2143 res_ctx->pipe_ctx[i].top_pipe->plane_res.scl_data.recout.height;
|
| dcn20_dpp.h | 697 struct scaler_data scl_data; member in struct:dcn20_dpp
750 const struct scaler_data *scl_data,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/ |
| amdgpu_dc_resource.c | 544 struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
659 pipe_ctx->plane_res.scl_data.recout.x = stream->dst.x;
661 pipe_ctx->plane_res.scl_data.recout.x += (surf_clip.x
665 pipe_ctx->plane_res.scl_data.recout.width = surf_clip.width *
667 if (pipe_ctx->plane_res.scl_data.recout.width + pipe_ctx->plane_res.scl_data.recout.x >
669 pipe_ctx->plane_res.scl_data.recout.width =
671 - pipe_ctx->plane_res.scl_data.recout.x;
673 pipe_ctx->plane_res.scl_data.recout.y = stream->dst.y;
675 pipe_ctx->plane_res.scl_data.recout.y += (surf_clip.
[all...] |
| amdgpu_dc.c | 470 pipes->plane_res.scl_data.lb_params.depth,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| amdgpu_dce_transform.c | 898 struct scaler_data *scl_data,
902 int pixel_width = scl_data->viewport.width;
906 (scl_data->viewport.width > scl_data->recout.width))
907 pixel_width = scl_data->recout.width;
911 scl_data->lb_params.depth,
927 scl_data->taps.h_taps = decide_taps(scl_data->ratios.horz, in_taps->h_taps, false);
928 scl_data->taps.v_taps = decide_taps(scl_data->ratios.vert, in_taps->v_taps, false)
[all...] |
| dce_transform.h | 496 struct scaler_data *scl_data,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/ |
| transform.h | 190 const struct scaler_data *scl_data);
199 struct scaler_data *scl_data,
301 const struct scaler_data *scl_data,
|
| dpp.h | 139 const struct scaler_data *scl_data);
148 struct scaler_data *scl_data,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/ |
| amdgpu_dcn_calcs.c | 338 input->src.viewport_width = pipe->plane_res.scl_data.viewport.width;
339 input->src.viewport_height = pipe->plane_res.scl_data.viewport.height;
340 input->src.data_pitch = pipe->plane_res.scl_data.viewport.width;
341 input->src.data_pitch_c = pipe->plane_res.scl_data.viewport.width;
389 input->scale_taps.htaps = pipe->plane_res.scl_data.taps.h_taps;
390 input->scale_ratio_depth.hscl_ratio = pipe->plane_res.scl_data.ratios.horz.value/4294967296.0;
391 input->scale_ratio_depth.vscl_ratio = pipe->plane_res.scl_data.ratios.vert.value/4294967296.0;
392 input->scale_ratio_depth.vinit = pipe->plane_res.scl_data.inits.v.value/4294967296.0;
395 input->scale_taps.vtaps = pipe->plane_res.scl_data.taps.v_taps;
396 input->scale_taps.vtaps_c = pipe->plane_res.scl_data.taps.v_taps_c
[all...] |
| amdgpu_dce_calcs.c | 2804 data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.width);
2806 data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.height);
2807 data->h_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.h_taps);
2808 data->v_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.v_taps);
2809 data->h_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.horz.value);
2810 data->v_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.vert.value);
2858 data->src_height[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.viewport.height);
2859 data->src_width[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.viewport.width);
2862 data->h_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.h_taps);
2863 data->v_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.v_taps)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/ |
| amdgpu_dce110_transform_v.c | 55 const struct scaler_data *scl_data,
60 luma_viewport->x = scl_data->viewport.x - scl_data->viewport.x % 2;
61 luma_viewport->y = scl_data->viewport.y - scl_data->viewport.y % 2;
63 scl_data->viewport.width - scl_data->viewport.width % 2;
65 scl_data->viewport.height - scl_data->viewport.height % 2;
71 if (scl_data->format == PIXEL_FORMAT_420BPP8)
[all...] |
| amdgpu_dce110_hw_sequencer.c | 1199 switch (pipe_ctx->plane_res.scl_data.format) {
1249 pipe_ctx->plane_res.scl_data.lb_params.depth,
1267 &pipe_ctx->plane_res.scl_data);
1421 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
2114 default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format;
2121 default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth;
2499 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
2558 pipe_ctx->plane_res.scl_data.viewport.width,
2559 pipe_ctx->plane_res.scl_data.viewport.height,
2560 pipe_ctx->plane_res.scl_data.viewport.x
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/ |
| core_types.h | 248 struct scaler_data scl_data; member in struct:plane_resource
|
