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  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/clk/
nouveau_nvkm_subdev_clk_gk104.c 73 u32 sclk; local in function:read_pll
82 sclk = device->crystal;
86 sclk = read_pll(clk, 0x132020);
90 sclk = read_div(clk, 0, 0x137320, 0x137330);
97 sclk = read_div(clk, (pll & 0xff) / 0x20, 0x137120, 0x137140);
106 sclk = (sclk * N) + (((u16)(fN + 4096) * sclk) >> 13);
107 return sclk / (M * P);
126 u32 sclk = read_vco(clk, dsrc + (doff * 4)) local in function:read_div
154 u32 sclk, sdiv; local in function:read_clk
241 u32 sclk; local in function:calc_src
    [all...]
nouveau_nvkm_subdev_clk_gf100.c 72 u32 sclk; local in function:read_pll
80 sclk = device->crystal;
84 sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrc);
87 sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrcref);
93 sclk = read_div(clk, (pll & 0xff) / 0x20, 0x137120, 0x137140);
99 return sclk * N / M / P;
107 u32 sclk, sctl, sdiv = 2; local in function:read_div
117 sclk = read_vco(clk, dsrc + (doff * 4));
131 return (sclk * 2) / sdiv;
143 u32 sclk, sdiv local in function:read_clk
228 u32 sclk; local in function:calc_src
    [all...]
nouveau_nvkm_subdev_clk_gt215.c 69 u32 sctl, sdiv, sclk; local in function:read_clk
104 sclk = read_vco(clk, idx);
106 return (sclk * 2) / sdiv;
117 u32 sclk = 0, P = 1, N = 1, M = 1; local in function:read_pll
133 sclk = read_clk(clk, 0x00 + idx, false);
136 sclk = read_clk(clk, 0x10 + idx, false);
144 return sclk * N / MP;
196 u32 oclk, sclk, sdiv; local in function:gt215_clk_info
212 sclk = read_vco(clk, idx);
213 sdiv = min((sclk * 2) / khz, (u32)65)
    [all...]
nouveau_nvkm_subdev_clk_nv40.c 155 int sclk = cstate->domain[nv_clk_src_shader]; local in function:nv40_clk_calc
174 if (sclk && sclk != gclk) {
175 ret = nv40_clk_calc_pll(clk, 0x004008, sclk,
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_rv730_dpm.c 46 RV770_SMC_SCLK_VALUE *sclk)
113 sclk->sclk_value = cpu_to_be32(engine_clock);
114 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
115 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2);
116 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);
117 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(cg_spll_spread_spectrum);
118 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(cg_spll_spread_spectrum_2);
309 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
310 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2);
311 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3)
    [all...]
radeon_rv770_dpm.c 276 a_n = (int)state->medium.sclk * pi->lmp +
277 (int)state->low.sclk * (R600_AH_DFLT - pi->rlp);
278 a_d = (int)state->low.sclk * (100 - (int)pi->rlp) +
279 (int)state->medium.sclk * pi->lmp;
284 a_n = (int)state->high.sclk * pi->lhp + (int)state->medium.sclk *
286 a_d = (int)state->medium.sclk * (100 - (int)pi->rmp) +
287 (int)state->high.sclk * pi->lhp;
490 RV770_SMC_SCLK_VALUE *sclk)
560 sclk->sclk_value = cpu_to_be32(engine_clock)
2185 u32 sclk, mclk; local in function:rv7xx_parse_pplib_clock_info
    [all...]
radeon_rv740_dpm.c 126 RV770_SMC_SCLK_VALUE *sclk)
181 sclk->sclk_value = cpu_to_be32(engine_clock);
182 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
183 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2);
184 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);
185 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(cg_spll_spread_spectrum);
186 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(cg_spll_spread_spectrum_2);
387 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
388 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2);
389 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3)
    [all...]
radeon_trinity_dpm.c 589 u32 index, u32 sclk)
597 sclk, false, &dividers);
607 sclk/2, false, &dividers);
727 trinity_set_divider_value(rdev, index, pl->sclk);
974 if (new_ps->levels[new_ps->num_levels - 1].sclk >=
975 current_ps->levels[current_ps->num_levels - 1].sclk)
988 if (new_ps->levels[new_ps->num_levels - 1].sclk <
989 current_ps->levels[current_ps->num_levels - 1].sclk)
1339 static u8 trinity_calculate_vce_wm(struct radeon_device *rdev, u32 sclk)
1341 if (sclk < 20000
1719 u32 sclk; local in function:trinity_parse_pplib_clock_info
1811 u32 sclk; local in function:trinity_parse_power_table
    [all...]
btc_dpm.h 48 u32 *sclk, u32 *mclk);
rv6xx_dpm.h 32 /* Represents a single SCLK step. */
82 u32 sclk; member in struct:rv6xx_pl
radeon_btc_dpm.c 1249 u32 *sclk, u32 *mclk)
1253 if ((sclk == NULL) || (mclk == NULL))
1259 if ((btc_blacklist_clocks[i].sclk == *sclk) &&
1266 *sclk = btc_get_valid_sclk(rdev, max_sclk, *sclk + 1);
1268 if (*sclk < max_sclk)
1269 btc_skip_blacklist_clocks(rdev, max_sclk, max_mclk, sclk, mclk);
1279 if ((pl->mclk == 0) || (pl->sclk == 0))
1282 if (pl->mclk == pl->sclk)
2106 u32 mclk, sclk; local in function:btc_apply_state_adjust_rules
    [all...]
radeon_ni_dpm.c 816 if (ps->performance_levels[i].sclk > max_limits->sclk)
817 ps->performance_levels[i].sclk = max_limits->sclk;
835 btc_skip_blacklist_clocks(rdev, max_limits->sclk, max_limits->mclk,
836 &ps->performance_levels[0].sclk,
840 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)
841 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;
2104 u32 sclk = 0; local in function:ni_init_smc_spll_table
    [all...]
radeon_sumo_dpm.c 352 u32 highest_engine_clock = ps->levels[ps->num_levels - 1].sclk;
355 highest_engine_clock = pi->boost_pl.sclk;
416 m_a = asi * ps->levels[i].sclk / 100;
426 m_a = asi * pi->boost_pl.sclk / 100;
560 pl->sclk, false, &dividers);
676 pi->boost_pl.sclk = pi->sys_info.boost_sclk;
795 pi->acpi_pl.sclk,
849 if (new_ps->levels[new_ps->num_levels - 1].sclk >=
850 current_ps->levels[current_ps->num_levels - 1].sclk)
867 if (new_ps->levels[new_ps->num_levels - 1].sclk <
1441 u32 sclk; local in function:sumo_parse_pplib_clock_info
    [all...]
radeon_kv_dpm.c 540 u32 index, u32 sclk)
547 sclk, false, &dividers);
552 pi->graphics_level[index].SclkFrequency = cpu_to_be32(sclk);
729 if (table->entries[i].clk == pi->boot_pl.sclk)
743 if (table->entries[i].sclk_frequency == pi->boot_pl.sclk)
1724 if ((table->entries[i].clk >= new_ps->levels[0].sclk) ||
1732 if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk)
1738 if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) >
1739 (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk))
1749 if (table->entries[i].sclk_frequency >= new_ps->levels[0].sclk ||
2152 u32 sclk, mclk = 0; local in function:kv_apply_state_adjust_rules
2624 u32 sclk; local in function:kv_parse_pplib_clock_info
2716 u32 sclk; local in function:kv_parse_power_table
2816 u32 sclk, tmp; local in function:kv_dpm_debugfs_print_current_performance_level
2840 u32 sclk; local in function:kv_dpm_get_current_sclk
    [all...]
radeon_rs690.c 274 fixed20_12 sclk; member in struct:rs690_watermark
286 fixed20_12 sclk, core_bandwidth, max_bandwidth; local in function:rs690_crtc_bandwidth_compute
301 /* sclk in Mhz */
303 sclk.full = dfixed_const(selected_sclk);
304 sclk.full = dfixed_div(sclk, a);
306 /* core_bandwidth = sclk(Mhz) * 16 */
308 core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
390 /* sclk = system clocks(ns) = 1000 / max_bandwidth / 16 */
392 sclk.full = dfixed_mul(max_bandwidth, a)
    [all...]
sumo_dpm.h 35 u32 sclk; member in struct:sumo_pl
210 u32 sclk,
radeon_rv6xx_dpm.c 444 state->low.sclk;
446 state->medium.sclk;
448 state->high.sclk;
1032 rv6xx_calculate_t(state->low.sclk,
1033 state->medium.sclk,
1040 rv6xx_calculate_t(state->medium.sclk,
1041 state->high.sclk,
1431 old_state->low.sclk,
1432 new_state->low.sclk,
1444 new_state->low.sclk,
1826 u32 sclk, mclk; local in function:rv6xx_parse_pplib_clock_info
    [all...]
rv770_dpm.h 145 u32 sclk; member in struct:rv7xx_pl
184 RV770_SMC_SCLK_VALUE *sclk);
205 RV770_SMC_SCLK_VALUE *sclk);
  /src/sys/arch/arm/dts/
rk3328-crypto.dtsi 15 clock-names = "hclk_master", "hclk_slave", "sclk";
  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
emev2.dtsi 163 clock-names = "sclk";
171 clock-names = "sclk";
179 clock-names = "sclk";
187 clock-names = "sclk";
195 clock-names = "sclk";
275 clock-names = "sclk";
286 clock-names = "sclk";
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/amlogic/
meson-g12.dtsi 21 clock-names = "mclk", "sclk", "lrclk";
32 clock-names = "mclk", "sclk", "lrclk";
43 clock-names = "mclk", "sclk", "lrclk";
208 clock-names = "pclk", "sclk", "sclk_sel",
224 clock-names = "pclk", "sclk", "sclk_sel",
240 clock-names = "pclk", "sclk", "sclk_sel",
256 clock-names = "pclk", "sclk", "sclk_sel",
298 clock-names = "pclk", "sclk", "sclk_sel",
313 clock-names = "pclk", "sclk", "sclk_sel",
328 clock-names = "pclk", "sclk", "sclk_sel"
    [all...]
meson-sm1.dtsi 23 clock-names = "mclk", "sclk", "lrclk";
34 clock-names = "mclk", "sclk", "lrclk";
45 clock-names = "mclk", "sclk", "lrclk";
306 clock-names = "pclk", "sclk", "sclk_sel",
322 clock-names = "pclk", "sclk", "sclk_sel",
338 clock-names = "pclk", "sclk", "sclk_sel",
354 clock-names = "pclk", "sclk", "sclk_sel",
369 clock-names = "pclk", "sclk", "sclk_sel",
384 clock-names = "pclk", "sclk", "sclk_sel",
399 clock-names = "pclk", "sclk", "sclk_sel"
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_kv_dpm.c 667 u32 index, u32 sclk)
674 sclk, false, &dividers);
679 pi->graphics_level[index].SclkFrequency = cpu_to_be32(sclk);
812 if (table->entries[i].clk == pi->boot_pl.sclk)
826 if (table->entries[i].sclk_frequency == pi->boot_pl.sclk)
1788 if ((table->entries[i].clk >= new_ps->levels[0].sclk) ||
1796 if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk)
1802 if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) >
1803 (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk))
1813 if (table->entries[i].sclk_frequency >= new_ps->levels[0].sclk ||
2217 u32 sclk, mclk = 0; local in function:kv_apply_state_adjust_rules
2692 u32 sclk; local in function:kv_parse_pplib_clock_info
2784 u32 sclk; local in function:kv_parse_power_table
2880 u32 sclk, tmp; local in function:kv_dpm_debugfs_print_current_performance_level
3293 uint32_t sclk; local in function:kv_dpm_read_sensor
    [all...]
amdgpu_si_dpm.c 1856 SISLANDS_SMC_SCLK_VALUE *sclk);
2427 prev_sclk = state->performance_levels[i-1].sclk;
2428 max_sclk = state->performance_levels[i].sclk;
2446 if (min_sclk < state->performance_levels[0].sclk)
2447 min_sclk = state->performance_levels[0].sclk;
2521 if ((state->performance_levels[i].sclk >= adev->pm.dpm.sq_ramping_threshold) &&
2959 u32 sclk = 0; local in function:si_init_smc_spll_table
2972 ret = si_calculate_sclk_params(adev, sclk, &sclk_params);
3004 sclk += 512;
3188 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk >
3439 u32 mclk, sclk; local in function:si_apply_state_adjust_rules
7295 u32 sclk, mclk; local in function:si_parse_power_table
7997 uint32_t sclk, mclk; local in function:si_dpm_read_sensor
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
power_state.h 178 unsigned long sclk; member in struct:pp_clock_engine_request

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