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    Searched refs:setDesc (Results 1 - 25 of 96) sorted by relevancy

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  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
WebAssemblyLowerBrUnless.cpp 81 Def->setDesc(TII.get(NE_I32));
85 Def->setDesc(TII.get(EQ_I32));
89 Def->setDesc(TII.get(LE_S_I32));
93 Def->setDesc(TII.get(LT_S_I32));
97 Def->setDesc(TII.get(GE_S_I32));
101 Def->setDesc(TII.get(GT_S_I32));
105 Def->setDesc(TII.get(LE_U_I32));
109 Def->setDesc(TII.get(LT_U_I32));
113 Def->setDesc(TII.get(GE_U_I32));
117 Def->setDesc(TII.get(GT_U_I32))
    [all...]
  /src/external/bsd/openldap/dist/contrib/ldapc++/src/
LDAPAttrType.h 92 void setDesc(const char *at_desc);
LDAPObjClass.h 99 void setDesc (char *oc_desc);
LDAPAttrType.cpp 34 this->setDesc( a->at_desc );
59 void LDAPAttrType::setDesc (const char *at_desc) {
LDAPObjClass.cpp 48 this->setDesc (o->oc_desc);
82 void LDAPObjClass::setDesc (char *oc_desc) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIOptimizeExecMasking.cpp 179 MI.setDesc(TII.get(RegSrc ? AMDGPU::COPY : AMDGPU::S_MOV_B32));
184 MI.setDesc(TII.get(RegSrc ? AMDGPU::COPY : AMDGPU::S_MOV_B64));
190 MI.setDesc(TII.get(AMDGPU::S_XOR_B64));
196 MI.setDesc(TII.get(AMDGPU::S_XOR_B32));
202 MI.setDesc(TII.get(AMDGPU::S_OR_B64));
208 MI.setDesc(TII.get(AMDGPU::S_OR_B32));
214 MI.setDesc(TII.get(AMDGPU::S_ANDN2_B64));
220 MI.setDesc(TII.get(AMDGPU::S_ANDN2_B32));
226 MI.setDesc(TII.get(AMDGPU::S_AND_B64));
232 MI.setDesc(TII.get(AMDGPU::S_AND_B32))
    [all...]
SIShrinkInstructions.cpp 200 MI.setDesc(TII->get(SOPKOpc));
210 MI.setDesc(NewDesc);
289 MI.setDesc(TII->get(NewOpcode));
368 MI.setDesc(TII->get(Opc));
627 MI.setDesc(TII->get(AMDGPU::V_BFREV_B32_e32));
672 MI.setDesc(TII->get(Opc));
692 MI.setDesc(TII->get(AMDGPU::S_MOVK_I32));
694 MI.setDesc(TII->get(AMDGPU::S_BREV_B32));
SIPreEmitPeephole.cpp 174 MI.setDesc(TII->get(AMDGPU::S_BRANCH));
202 MI.setDesc(TII->get(AMDGPU::S_BRANCH));
212 MI.setDesc(
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZShortenInst.cpp 95 MI.setDesc(TII->get(LLIxL));
100 MI.setDesc(TII->get(LLIxH));
111 MI.setDesc(TII->get(Opcode));
122 MI.setDesc(TII->get(Opcode));
135 MI.setDesc(TII->get(Opcode));
168 MI.setDesc(TII->get(Opcode));
195 MI.setDesc(TII->get(Opcode));
365 MI.setDesc(TII->get(TwoOperandOpcode));
SystemZPostRewrite.cpp 95 MBBI->setDesc(TII->get(LowOpcode));
97 MBBI->setDesc(TII->get(HighOpcode));
146 MBBI->setDesc(TII->get(LowOpcode));
148 MBBI->setDesc(TII->get(HighOpcode));
223 MI.setDesc(TII->get(TargetMemOpcode));
SystemZElimCompare.cpp 229 Branch->setDesc(TII->get(BRCT));
272 Branch->setDesc(TII->get(LATOpcode));
332 MI.setDesc(TII->get(ConvOpc));
671 Branch->setDesc(TII->get(FusedOpcode));
SystemZInstrInfo.cpp 111 EarlierMI->setDesc(get(HighOpcode));
112 MI->setDesc(get(LowOpcode));
127 MI->setDesc(get(NewOpcode));
142 MI.setDesc(get(IsHigh ? HighOpcode : LowOpcode));
159 MI.setDesc(get(LowOpcodeK));
167 MI.setDesc(get(DestIsHigh ? HighOpcode : LowOpcode));
181 MI.setDesc(get(Opcode));
191 MI.setDesc(get(Opcode));
236 MI->setDesc(get(SystemZ::LG));
663 UseMI.setDesc(get(NewUseOpc))
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
ExpandPostRAPseudos.cpp 99 MI->setDesc(TII->get(TargetOpcode::KILL));
112 MI->setDesc(TII->get(TargetOpcode::KILL));
139 MI->setDesc(TII->get(TargetOpcode::KILL));
156 MI->setDesc(TII->get(TargetOpcode::KILL));
ProcessImplicitDefs.cpp 88 UserMI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMInstructionSelector.cpp 256 MIB->setDesc(TII.get(ARM::VMOVDRR));
288 MIB->setDesc(TII.get(ARM::VMOVRRD));
677 MIB->setDesc(TII.get(Opc));
715 MIB->setDesc(TII.get(Opc));
735 MIB->setDesc(TII.get(Opcodes.ADDrr));
747 MIB->setDesc(TII.get(Opcodes.MOVi32imm));
750 MIB->setDesc(TII.get(Opcodes.ConstPoolLoad));
756 MIB->setDesc(TII.get(Opcodes.MOVi32imm));
758 MIB->setDesc(TII.get(Opcodes.LDRLIT_ga_abs));
807 MIB->setDesc(TII.get(ARM::MOVsr))
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64CompressJumpTables.cpp 147 MI.setDesc(TII->get(AArch64::JumpTableDest8));
153 MI.setDesc(TII->get(AArch64::JumpTableDest16));
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCEarlyReturn.cpp 94 MI->setDesc(TII->get(PPC::BCCLR));
111 MI->setDesc(
  /src/external/apache2/llvm/dist/llvm/include/llvm/MC/
MCSymbolMachO.h 105 void setDesc(unsigned Value) const {
  /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
DelaySlotFiller.cpp 188 slot->setDesc(Subtarget->getInstrInfo()->get(SP::RET));
391 AddMI->setDesc(TII->get((AddMI->getOpcode() == SP::ADDrr)
430 OrMI->setDesc(TII->get((OrMI->getOpcode() == SP::ORrr)
467 RestoreMI->setDesc(TII->get(SP::RESTOREri));
SparcRegisterInfo.cpp 192 MI.setDesc(TII.get(SP::STDFri));
205 MI.setDesc(TII.get(SP::LDDFri));
  /src/external/apache2/llvm/dist/llvm/lib/Target/VE/
VERegisterInfo.cpp 175 MI.setDesc(TII.get(VE::STrii));
190 MI.setDesc(TII.get(VE::LDrii));
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86InstructionSelector.cpp 305 I.setDesc(TII.get(X86::COPY));
537 I.setDesc(TII.get(NewOpc));
573 I.setDesc(TII.get(NewOpc));
625 I.setDesc(TII.get(NewOpc));
677 I.setDesc(TII.get(NewOpc));
702 I.setDesc(TII.get(X86::COPY));
768 I.setDesc(TII.get(X86::COPY));
877 I.setDesc(TII.get(X86::COPY));
1128 I.setDesc(TII.get(X86::VEXTRACTF32x4Z256rr));
1130 I.setDesc(TII.get(X86::VEXTRACTF128rr))
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64PostSelectOptimize.cpp 151 II.setDesc(TII->get(NewOpc));
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonCFGOptimizer.cpp 103 MI.setDesc(TII->get(NewOpcode));
  /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/
MSP430RegisterInfo.cpp 135 MI.setDesc(TII.get(MSP430::MOV16rr));

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