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    Searched refs:setIsUndef (Results 1 - 25 of 29) sorted by relevancy

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  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
ProcessImplicitDefs.cpp 83 MO.setIsUndef();
111 MO.setIsUndef();
DetectDeadLanes.cpp 551 MO.setIsUndef();
555 MO.setIsUndef();
VirtRegMap.cpp 577 MO.setIsUndef(true);
588 MO.setIsUndef(false);
RenameIndependentSubregs.cpp 357 MO.setIsUndef();
RegisterCoalescer.cpp 1358 DefMO.setIsUndef(false); // Only subregs can have def+undef.
1423 NewMI.getOperand(0).setIsUndef(false);
1526 NewMI.getOperand(0).setIsUndef();
1675 MO.setIsUndef(true);
1686 MO.setIsUndef(true);
1707 MO.setIsUndef(true);
1767 MO.setIsUndef(!Reads);
1855 MO.setIsUndef();
3087 MO.setIsUndef(false);
TargetInstrInfo.cpp 237 CommutedMI->getOperand(Idx2).setIsUndef(Reg1IsUndef);
238 CommutedMI->getOperand(Idx1).setIsUndef(Reg2IsUndef);
PeepholeOptimizer.cpp 595 Copy->getOperand(0).setIsUndef();
1247 NewCopy->getOperand(0).setIsUndef();
TwoAddressInstructionPass.cpp 1622 mi->getOperand(0).setIsUndef(mi->getOperand(1).isUndef());
1698 CopyMI->getOperand(0).setIsUndef(true);
MachineOperand.cpp 95 setIsUndef(false);
ScheduleDAGInstrs.cpp 423 MO.setIsUndef(false);
BranchFolding.cpp 799 MO.setIsUndef(false);
InlineSpiller.cpp 592 MO.setIsUndef();
MachineInstr.cpp 2022 MO.setIsUndef(IsUndef);
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCVSXFMAMutate.cpp 257 MI.getOperand(1).setIsUndef(KilledProdRegUndef);
258 MI.getOperand(3).setIsUndef(AddRegUndef);
268 MI.getOperand(2).setIsUndef(AddRegUndef);
273 MI.getOperand(2).setIsUndef(OtherProdRegUndef);
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
MachineOperand.h 511 void setIsUndef(bool Val = true) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
GCNDPPCombine.cpp 598 S.first->getOperand(S.second.pop_back_val()).setIsUndef(true);
GCNIterativeScheduler.cpp 377 Op.setIsUndef(false);
GCNSchedStrategy.cpp 431 Op.setIsUndef(false);
SIShrinkInstructions.cpp 291 MI.getOperand(VAddr0Idx).setIsUndef(IsUndef);
SIPeepholeSDWA.cpp 249 To.setIsUndef(From.isUndef());
SIInstrInfo.cpp 1850 SetOn->getOperand(3).setIsUndef();
1890 SetOn->getOperand(3).setIsUndef();
2414 CondReg.setIsUndef(OrigCond.isUndef());
2469 CondReg.setIsUndef(Cond[1].isUndef());
3558 Use.setIsUndef(Orig.isUndef());
6153 NewSelect->getOperand(3).setIsUndef(Cond.isUndef());
SIFoldOperands.cpp 319 Old.setIsUndef(New->isUndef());
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonOptAddrMode.cpp 423 BaseOp.setIsUndef(AddRegOp.isUndef());
  /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
AVRExpandPseudoInsts.cpp 1787 ->getOperand(3).setIsUndef(true);
1825 ->getOperand(4).setIsUndef(true);
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMLoadStoreOptimizer.cpp 949 MO.setIsUndef();

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