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  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCVSXFMAMutate.cpp 250 MI.getOperand(0).setSubReg(KilledProdSubReg);
251 MI.getOperand(1).setSubReg(KilledProdSubReg);
252 MI.getOperand(3).setSubReg(AddSubReg);
266 MI.getOperand(2).setSubReg(AddSubReg);
271 MI.getOperand(2).setSubReg(OtherProdSubReg);
PPCVSXCopy.cpp 134 SrcMO.setSubReg(PPC::sub_64);
PPCInstrInfo.cpp 1211 MI.getOperand(0).setSubReg(SubReg2);
1215 MI.getOperand(2).setSubReg(SubReg1);
1216 MI.getOperand(1).setSubReg(SubReg2);
2731 SubRegsToUpdate[i].first->setSubReg(SubRegsToUpdate[i].second);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIPreAllocateWWMRegs.cpp 135 MO.setSubReg(0);
SIFoldOperands.cpp 745 UseMI->getOperand(1).setSubReg(OpToFold.getSubReg());
883 UseMI->getOperand(1).setSubReg(OpToFold.getSubReg());
SIPeepholeSDWA.cpp 248 To.setSubReg(From.getSubReg());
SIInstrInfo.cpp 2064 NonRegOp.setSubReg(SubReg);
2746 UseMI.getOperand(0).setSubReg(0);
2816 Src0->setSubReg(Src1SubReg);
4824 Src0.setSubReg(Src1.getSubReg());
4829 Src1.setSubReg(Src0SubReg);
5103 Op.setSubReg(0);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
RDFCopy.cpp 181 Op.setSubReg(0);
HexagonExpandCondsets.cpp 926 Op.setSubReg(RN.Sub);
HexagonBitSimplify.cpp 380 I->setSubReg(NewSR);
399 I->setSubReg(NewSR);
1941 ValOp.setSubReg(H.Sub);
HexagonHardwareLoops.cpp 1920 MO.setSubReg(PredRSub);
HexagonSplitDouble.cpp 1092 Op.setSubReg(0);
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
MachineOperand.h 471 void setSubReg(unsigned subReg) {
813 Op.setSubReg(SubReg);
MachineInstr.h 1847 MO.setSubReg(0);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
RegAllocFast.cpp 838 MO.setSubReg(0);
994 MO.setSubReg(0);
1254 MO.setSubReg(0);
1357 MO.setSubReg(0);
PeepholeOptimizer.cpp 594 Copy->getOperand(0).setSubReg(SubIdx);
863 MOSrc.setSubReg(NewSubReg);
953 MO.setSubReg(NewSubReg);
1080 MO.setSubReg(NewSubReg);
1246 NewCopy->getOperand(0).setSubReg(Def.SubReg);
TargetInstrInfo.cpp 229 CommutedMI->getOperand(0).setSubReg(SubReg0);
233 CommutedMI->getOperand(Idx2).setSubReg(SubReg1);
234 CommutedMI->getOperand(Idx1).setSubReg(SubReg2);
TwoAddressInstructionPass.cpp 1345 SrcMO.setSubReg(0);
1458 MO.setSubReg(0);
1476 MO.setSubReg(0);
1621 mi->getOperand(0).setSubReg(SubIdx);
VirtRegMap.cpp 595 MO.setSubReg(0);
MachineOperand.cpp 84 setSubReg(SubIdx);
93 setSubReg(0);
MachineSink.cpp 1078 DbgMO.setSubReg(SrcMO->getSubReg());
1483 DbgOp.setSubReg(MI.getOperand(1).getSubReg());
LiveDebugVariables.cpp 1305 MO.setSubReg(locations[OldLocNo].getSubReg());
1448 Loc.setSubReg(0);
TailDuplicator.cpp 436 MO.setSubReg(TRI->composeSubRegIndices(MO.getSubReg(),
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86DomainReassignment.cpp 512 MO.setSubReg(0);
X86InstructionSelector.cpp 289 I.getOperand(1).setSubReg(getSubRegIndex(DstRC));
766 I.getOperand(1).setSubReg(SubIdx);

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