| /src/sys/external/bsd/drm2/dist/drm/amd/amdkfd/ |
| kfd_device_queue_manager_v10.c | 81 qpd->sh_mem_bases = compute_sh_mem_bases_64bit(pdd);
83 pr_debug("sh_mem_bases 0x%X\n", qpd->sh_mem_bases);
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| kfd_device_queue_manager_v9.c | 78 qpd->sh_mem_bases = compute_sh_mem_bases_64bit(pdd);
80 pr_debug("sh_mem_bases 0x%X\n", qpd->sh_mem_bases);
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| kfd_device_queue_manager_cik.c | 81 * top 3 bits of SH_MEM_BASES.PRIVATE_BASE.
83 * top 3 bits of SH_MEM_BASES.SHARED_BASE.
141 qpd->sh_mem_bases = SHARED_BASE(temp);
145 qpd->sh_mem_bases = compute_sh_mem_bases_64bit(temp);
149 pr_debug("is32bit process: %d sh_mem_bases nybble: 0x%X and register 0x%X\n",
150 qpd->pqm->process->is_32bit_user_mode, temp, qpd->sh_mem_bases);
177 qpd->sh_mem_bases = compute_sh_mem_bases_64bit(temp);
179 pr_debug("is32bit process: %d sh_mem_bases nybble: 0x%X and register 0x%X\n",
180 qpd->pqm->process->is_32bit_user_mode, temp, qpd->sh_mem_bases);
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| kfd_device_queue_manager_vi.c | 87 * top 3 bits of SH_MEM_BASES.PRIVATE_BASE.
89 * top 3 bits of SH_MEM_BASES.SHARED_BASE.
181 qpd->sh_mem_bases = temp << SH_MEM_BASES__SHARED_BASE__SHIFT;
186 qpd->sh_mem_bases = compute_sh_mem_bases_64bit(temp);
193 pr_debug("is32bit process: %d sh_mem_bases nybble: 0x%X and register 0x%X\n",
194 qpd->pqm->process->is_32bit_user_mode, temp, qpd->sh_mem_bases);
225 qpd->sh_mem_bases = compute_sh_mem_bases_64bit(temp);
227 pr_debug("sh_mem_bases nybble: 0x%X and register 0x%X\n",
228 temp, qpd->sh_mem_bases);
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| kfd_pm4_headers.h | 76 uint32_t sh_mem_bases; member in struct:pm4_map_process
126 uint32_t sh_mem_bases; member in struct:pm4_map_process_scratch_kv
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| kfd_packet_manager_v9.c | 57 packet->sh_mem_bases = qpd->sh_mem_bases;
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| kfd_packet_manager_vi.c | 67 packet->sh_mem_bases = qpd->sh_mem_bases;
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| kfd_pm4_headers_vi.h | 173 uint32_t sh_mem_bases; member in struct:pm4_mes_map_process
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| kfd_pm4_headers_ai.h | 161 uint32_t sh_mem_bases; member in struct:pm4_mes_map_process
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| kfd_priv.h | 568 uint32_t sh_mem_bases; member in struct:qcm_process_device
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| kfd_device_queue_manager.c | 137 qpd->sh_mem_bases);
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| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_amdkfd_gfx_v9.h | 30 uint32_t sh_mem_bases);
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| amdgpu_amdkfd_gfx_v10.c | 133 uint32_t sh_mem_bases)
140 WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases);
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| amdgpu_amdkfd_gfx_v7.c | 160 uint32_t sh_mem_bases)
169 WREG32(mmSH_MEM_BASES, sh_mem_bases);
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| amdgpu_amdkfd_gfx_v8.c | 117 uint32_t sh_mem_bases)
126 WREG32(mmSH_MEM_BASES, sh_mem_bases);
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| amdgpu_amdkfd_gfx_v9.c | 129 uint32_t sh_mem_bases)
136 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases);
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| amdgpu_gfx_v10_0.c | 1602 uint32_t sh_mem_bases; local in function:gfx_v10_0_init_compute_vmid
1610 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1617 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
1755 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
1757 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
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| amdgpu_gfx_v7_0.c | 1867 uint32_t sh_mem_bases; local in function:gfx_v7_0_init_compute_vmid
1875 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1886 WREG32(mmSH_MEM_BASES, sh_mem_bases);
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| amdgpu_gfx_v8_0.c | 3688 uint32_t sh_mem_bases; local in function:gfx_v8_0_init_compute_vmid
3696 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
3712 WREG32(mmSH_MEM_BASES, sh_mem_bases);
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| amdgpu_gfx_v9_0.c | 2406 uint32_t sh_mem_bases; local in function:gfx_v9_0_init_compute_vmid
2414 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
2425 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
2506 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
2508 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
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| /src/sys/external/bsd/drm2/dist/drm/amd/include/ |
| kgd_kfd_interface.h | 249 uint32_t sh_mem_ape1_limit, uint32_t sh_mem_bases);
|
