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  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/
hw_ddc.h 36 const struct ddc_sh_mask *shifts; member in struct:hw_ddc
hw_generic.h 37 const struct generic_sh_mask *shifts; member in struct:hw_generic
hw_hpd.h 36 const struct hpd_sh_mask *shifts; member in struct:hw_hpd
amdgpu_hw_generic.c 45 generic->shifts->field_name, generic->masks->field_name
amdgpu_hw_hpd.c 45 hpd->shifts->field_name, hpd->masks->field_name
  /src/sys/arch/hpc/hpc/
platid.awk 70 mode_name[mode], nm, saved_name, shifts[mode, nest]) > out_h
140 shifts[CPU, 0] = "PLATID_CPU_ARCH_SHIFT"
141 shifts[CPU, 1] = "PLATID_CPU_SERIES_SHIFT"
142 shifts[CPU, 2] = "PLATID_CPU_MODEL_SHIFT"
143 shifts[CPU, 3] = "PLATID_CPU_SUBMODEL_SHIFT"
145 shifts[MACH, 0] = "PLATID_VENDOR_SHIFT"
146 shifts[MACH, 1] = "PLATID_SERIES_SHIFT"
147 shifts[MACH, 2] = "PLATID_MODEL_SHIFT"
148 shifts[MACH, 3] = "PLATID_SUBMODEL_SHIFT"
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
dcn10_cm_common.h 72 struct xfer_func_shift shifts; member in struct:xfer_func_reg
87 struct cm_color_matrix_shift shifts; member in struct:color_matrices_reg
amdgpu_dcn10_dpp_cm.c 123 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11;
125 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12;
218 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_OCSC_C11;
220 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_OCSC_C12;
265 reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET;
267 reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
269 reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET;
271 reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
274 reg->shifts.field_region_end = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_B;
276 reg->shifts.field_region_end_slope = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
amdgpu_dce_i2c_hw.c 46 dce_i2c_hw->shifts->field_name, dce_i2c_hw->masks->field_name
603 const struct dce_i2c_shift *shifts,
610 dce_i2c_hw->shifts = shifts;
626 const struct dce_i2c_shift *shifts,
633 shifts,
643 const struct dce_i2c_shift *shifts,
650 shifts,
660 const struct dce_i2c_shift *shifts,
667 shifts,
    [all...]
dce_i2c_hw.h 274 const struct dce_i2c_shift *shifts; member in struct:dce_i2c_hw
283 const struct dce_i2c_shift *shifts,
291 const struct dce_i2c_shift *shifts,
299 const struct dce_i2c_shift *shifts,
307 const struct dce_i2c_shift *shifts,
315 const struct dce_i2c_shift *shifts,
dce_audio.h 129 const struct dce_audio_shift *shifts; member in struct:dce_audio
137 const struct dce_audio_shift *shifts,
amdgpu_dce_audio.c 51 aud->shifts->field_name, aud->masks->field_name
944 const struct dce_audio_shift *shifts,
960 audio->shifts = shifts;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_mpc.c 170 ocsc_regs.shifts.csc_c11 = mpc20->mpc_shift->MPC_OCSC_C11_A;
172 ocsc_regs.shifts.csc_c12 = mpc20->mpc_shift->MPC_OCSC_C12_A;
228 ocsc_regs.shifts.csc_c11 = mpc20->mpc_shift->MPC_OCSC_C11_A;
230 ocsc_regs.shifts.csc_c12 = mpc20->mpc_shift->MPC_OCSC_C12_A;
256 reg->shifts.exp_region0_lut_offset = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET;
258 reg->shifts.exp_region0_num_segments = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
260 reg->shifts.exp_region1_lut_offset = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET;
262 reg->shifts.exp_region1_num_segments = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
264 reg->shifts.field_region_end = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_END_B;
266 reg->shifts.field_region_end_slope = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B
    [all...]
amdgpu_dcn20_vmid.c 44 vmid->shifts->field_name, vmid->masks->field_name
dcn20_vmid.h 86 const struct dcn20_vmid_shift *shifts; member in struct:dcn20_vmid
amdgpu_dcn20_dpp_cm.c 194 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11;
196 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12;
289 icsc_regs.shifts.csc_c11 = dpp->tf_shift->CM_ICSC_C11;
291 icsc_regs.shifts.csc_c12 = dpp->tf_shift->CM_ICSC_C12;
367 reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET;
369 reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
371 reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET;
373 reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
376 reg->shifts.field_region_end = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_B;
378 reg->shifts.field_region_end_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B
    [all...]
dcn20_hubbub.h 81 const struct dcn_hubbub_shift *shifts; member in struct:dcn20_hubbub
amdgpu_dcn20_hubbub.c 44 hubbub1->shifts->field_name, hubbub1->masks->field_name
54 hubbub1->shifts->field_name, hubbub1->masks->field_name
627 hubbub->shifts = hubbub_shift;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dcn10/
amdgpu_hw_factory_dcn10.c 161 generic->shifts = &generic_shift[en];
186 ddc->shifts = &ddc_shift;
196 hpd->shifts = &hpd_shift;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dcn20/
amdgpu_hw_factory_dcn20.c 204 ddc->shifts = &ddc_shift[en];
214 hpd->shifts = &hpd_shift;
224 generic->shifts = &generic_shift[en];
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dcn21/
amdgpu_hw_factory_dcn21.c 169 generic->shifts = &generic_shift[en];
194 ddc->shifts = &ddc_shift[en];
204 hpd->shifts = &hpd_shift;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dce110/
amdgpu_hw_factory_dce110.c 141 ddc->shifts = &ddc_shift;
151 hpd->shifts = &hpd_shift;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dce80/
amdgpu_hw_factory_dce80.c 141 ddc->shifts = &ddc_shift;
151 hpd->shifts = &hpd_shift;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dce120/
amdgpu_hw_factory_dce120.c 154 ddc->shifts = &ddc_shift;
164 hpd->shifts = &hpd_shift;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/
amdgpu_dcn21_hwseq.c 51 hws->shifts->field_name, hws->masks->field_name

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