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    Searched refs:skl (Results 1 - 6 of 6) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/i915/display/
intel_atomic_plane.c 336 if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_y[plane_id],
339 skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_uv[plane_id],
345 entries_y[plane_id] = crtc_state->wm.skl.plane_ddb_y[plane_id];
346 entries_uv[plane_id] = crtc_state->wm.skl.plane_ddb_uv[plane_id];
388 memcpy(entries_y, old_crtc_state->wm.skl.plane_ddb_y,
389 sizeof(old_crtc_state->wm.skl.plane_ddb_y));
390 memcpy(entries_uv, old_crtc_state->wm.skl.plane_ddb_uv,
391 sizeof(old_crtc_state->wm.skl.plane_ddb_uv));
intel_display_types.h 743 } skl; member in union:intel_crtc_wm_state::__anonde7c4d45070a
intel_display.c 2775 * Display WA #0531: skl,bxt,kbl,glk
5881 * The same behaviour is observed on pre-SKL platforms as well.
13781 sw_wm = &new_crtc_state->wm.skl.optimal;
13831 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[plane];
13883 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR];
15141 entries[i] = old_crtc_state->wm.skl.ddb;
15169 if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
15173 entries[i] = new_crtc_state->wm.skl.ddb;
15185 if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
15186 &old_crtc_state->wm.skl.ddb) &
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/i915/
intel_pm.c 62 * WaCompressedResourceDisplayNewHashMode:skl,kbl
63 * Display WA #0390: skl,kbl
73 /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
77 /* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */
81 /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl,cfl */
82 /* WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl */
87 /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cfl */
2868 "SKL Mailbox read error = %d\n", ret);
2887 "SKL Mailbox read error = %d\n", ret);
2913 * WaWmMemoryReadLatency:skl+,gl
    [all...]
i915_debugfs.c 2111 * SKL+ Perf counter is reset to 0 everytime DC state is entered
2893 entry = &crtc_state->wm.skl.plane_ddb_y[plane_id];
2899 entry = &crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR];
  /src/sys/external/bsd/drm2/dist/drm/i915/gt/uc/
intel_uc_fw.c 59 fw_def(SKYLAKE, 0, guc_def(skl, 33, 0, 0), huc_def(skl, 2, 0, 0))

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