| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dsc/ |
| rc_calc.h | 82 void calc_rc_params(struct rc_params *rc, enum colour_mode cm, enum bits_per_comp bpc, float bpp, int slice_width, int slice_height, int minor_version);
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| amdgpu_rc_calc_dpi.c | 43 to->slice_height = from->slice_height;
116 int slice_height = pps->slice_height; local
135 calc_rc_params(&rc, mode, bpc, bpp, slice_width, slice_height, pps->dsc_version_minor);
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| amdgpu_dc_dsc.c | 579 int slice_height; local
742 slice_height = min(policy.min_slice_height, pic_height);
744 slice_height = min(min_slice_height_override, pic_height);
746 while (slice_height < pic_height && (pic_height % slice_height != 0 ||
747 (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420 && slice_height % 2 != 0)))
748 slice_height++;
751 is_dsc_possible = (slice_height % 2 == 0);
756 dsc_cfg->num_slices_v = pic_height/slice_height;
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| amdgpu_rc_calc.c | 180 void calc_rc_params(struct rc_params *rc, enum colour_mode cm, enum bits_per_comp bpc, float bpp, int slice_width, int slice_height, int minor_version)
195 rc->first_line_bpg_offset = median3(0, (12 + (int) (0.09 * min(34, slice_height - 8))), (int)((3 * bpc * 3) - (3 * bpp_group)));
200 rc->first_line_bpg_offset = median3(0, (12 + (int) (0.09 * min(34, slice_height - 8))), (int)((3 * bpc * 4) - (3 * bpp_group)));
206 rc->first_line_bpg_offset = median3(0, (12 + (int) (0.09 * min(34, slice_height - 8))), (int)(((3 * bpc + (cm == CM_444 ? 0 : 2)) * 3) - (3 * bpp_group)));
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| /src/sys/external/bsd/drm2/dist/drm/ |
| drm_dsc.c | 125 pps_payload->slice_height = cpu_to_be16(dsc_cfg->slice_height);
305 slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height;
332 if (vdsc_cfg->slice_height > 1)
339 (vdsc_cfg->slice_height - 1));
344 groups_total = groups_per_line * vdsc_cfg->slice_height;
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| /src/sys/external/bsd/drm2/dist/include/drm/ |
| drm_dsc.h | 102 * @slice_height: Slice height in pixels
104 u16 slice_height; member in struct:drm_dsc_config
351 * @slice_height:
354 __be16 slice_height; member in struct:drm_dsc_picture_parameter_set
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_dsc.c | 295 DC_LOG_DSC("\tslice_height %d", pps->slice_height);
381 dsc_reg_vals->pps.slice_height = dsc_cfg->pic_height / dsc_cfg->dc_dsc_cfg.num_slices_v;
383 ASSERT(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height);
384 if (!(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height)) {
503 reg_vals->pps.slice_height = 0;
606 SLICE_HEIGHT, reg_vals->pps.slice_height);
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| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_vdsc.c | 583 pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) |
751 vdsc_cfg->slice_height);
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| intel_vbt_defs.h | 890 u16 slice_height; member in struct:dsc_compression_parameters_entry
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| icl_dsi.c | 1368 WARN_ON(vdsc_cfg->slice_height < 8);
1369 WARN_ON(vdsc_cfg->pic_height % vdsc_cfg->slice_height);
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| intel_bios.c | 2487 vdsc_cfg->slice_height = dsc->slice_height;
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| intel_dp.c | 2079 vdsc_cfg->slice_height = 8;
2081 vdsc_cfg->slice_height = 4;
2083 vdsc_cfg->slice_height = 2;
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| /src/sys/external/bsd/drm2/dist/drm/i915/ |
| i915_reg.h | 11814 #define DSC_SLICE_HEIGHT(slice_height) ((slice_height) << 0)
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