| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dsc/ |
| rc_calc.h | 82 void calc_rc_params(struct rc_params *rc, enum colour_mode cm, enum bits_per_comp bpc, float bpp, int slice_width, int slice_height, int minor_version);
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| amdgpu_rc_calc_dpi.c | 42 to->slice_width = from->slice_width;
115 int slice_width = pps->slice_width; local in function:dscc_compute_dsc_parameters
121 double d_bytes_per_pixel = dsc_ceil(bpp * slice_width / 8.0) / slice_width;
135 calc_rc_params(&rc, mode, bpc, bpp, slice_width, slice_height, pps->dsc_version_minor);
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| amdgpu_rc_calc.c | 180 void calc_rc_params(struct rc_params *rc, enum colour_mode cm, enum bits_per_comp bpc, float bpp, int slice_width, int slice_height, int minor_version)
215 slice_width /= 2;
217 padding_pixels = ((slice_width % 3) != 0) ? (3 - (slice_width % 3)) * (rc->initial_xmit_delay / slice_width) : 0;
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| amdgpu_dc_dsc.c | 573 int slice_width; local in function:setup_dsc_config
733 slice_width = pic_width / num_slices_h;
735 is_dsc_possible = slice_width <= dsc_common_caps.max_slice_width;
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| /src/sys/external/bsd/drm2/dist/drm/ |
| drm_dsc.c | 128 pps_payload->slice_width = cpu_to_be16(dsc_cfg->slice_width);
274 groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width / 2,
278 vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width / 2 *
283 groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width,
287 vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width *
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/ |
| dsc.h | 50 uint32_t slice_width; /* Slice width in pixels */ member in struct:dsc_optc_config
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| /src/sys/external/bsd/drm2/dist/include/drm/ |
| drm_dsc.h | 98 * @slice_width: Width of each slice in pixels
100 u16 slice_width; member in struct:drm_dsc_config
356 * @slice_width:
359 __be16 slice_width; member in struct:drm_dsc_picture_parameter_set
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_dsc.c | 163 REG_GET(DSCC_PPS_CONFIG3, SLICE_WIDTH, &s->dsc_slice_width);
296 DC_LOG_DSC("\tslice_width %d", pps->slice_width);
379 // see what happens when the same condition doesn't apply for slice_width/pic_width.
380 dsc_reg_vals->pps.slice_width = dsc_cfg->pic_width / dsc_cfg->dc_dsc_cfg.num_slices_h;
408 dsc_optc_cfg->slice_width = dsc_reg_vals->pps.slice_width;
502 reg_vals->pps.slice_width = 0;
605 SLICE_WIDTH, reg_vals->pps.slice_width,
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/ |
| amdgpu_dc_link_hwss.c | 397 DC_LOG_DSC("\tslice_width %d", config->slice_width);
461 dsc_optc_cfg.slice_width);
472 dsc_optc_cfg.slice_width);
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| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_vdsc.c | 397 vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
584 DSC_SLICE_WIDTH(vdsc_cfg->slice_width);
749 vdsc_cfg->slice_width) |
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| icl_dsi.c | 1367 WARN_ON(vdsc_cfg->pic_width % vdsc_cfg->slice_width);
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| /src/sys/external/bsd/drm2/dist/drm/i915/ |
| i915_reg.h | 11813 #define DSC_SLICE_WIDTH(slice_width) ((slice_width) << 16)
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