| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/xilinx/ |
| zynqmp.dtsi | 275 iommus = <&smmu 0x14e8>;
288 iommus = <&smmu 0x14e9>;
301 iommus = <&smmu 0x14ea>;
314 iommus = <&smmu 0x14eb>;
327 iommus = <&smmu 0x14ec>;
340 iommus = <&smmu 0x14ed>;
353 iommus = <&smmu 0x14ee>;
366 iommus = <&smmu 0x14ef>;
396 iommus = <&smmu 0x868>;
409 iommus = <&smmu 0x869>
716 smmu: iommu@fd800000 { label
[all...] |
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/amd/ |
| amd-seattle-xgbe-b.dtsi | 88 xgmac0_smmu: smmu@e0600000 {
104 xgmac1_smmu: smmu@e0800000 {
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/arm/ |
| fvp-base-revc.dts | 170 iommu-map = <0x0 &smmu 0x0 0x10000>;
175 smmu: iommu@2b400000 { label
176 compatible = "arm,smmu-v3";
|
| juno-base.dtsi | 36 compatible = "arm,mmu-400", "arm,smmu-v1";
48 compatible = "arm,mmu-401", "arm,smmu-v1";
59 compatible = "arm,mmu-401", "arm,smmu-v1";
509 /* The SMMU is only really of interest to bare-metal hypervisors */
638 compatible = "arm,mmu-401", "arm,smmu-v1";
648 compatible = "arm,mmu-401", "arm,smmu-v1";
657 compatible = "arm,mmu-401", "arm,smmu-v1";
666 compatible = "arm,mmu-401", "arm,smmu-v1";
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/altera/ |
| socfpga_stratix10.dtsi | 153 iommus = <&smmu 1>;
171 iommus = <&smmu 2>;
189 iommus = <&smmu 3>;
301 iommus = <&smmu 5>;
353 smmu: iommu@fa000000 { label
354 compatible = "arm,mmu-500", "arm,smmu-v2";
487 iommus = <&smmu 6>;
500 iommus = <&smmu 7>;
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/intel/ |
| socfpga_agilex.dtsi | 165 iommus = <&smmu 1>;
183 iommus = <&smmu 2>;
201 iommus = <&smmu 3>;
315 iommus = <&smmu 5>;
367 smmu: iommu@fa000000 { label
368 compatible = "arm,mmu-500", "arm,smmu-v2";
513 iommus = <&smmu 6>;
525 iommus = <&smmu 7>;
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/nvidia/ |
| tegra194.dtsi | 65 iommus = <&smmu TEGRA194_SID_EQOS>;
737 iommus = <&smmu TEGRA194_SID_SDMMC1>;
764 iommus = <&smmu TEGRA194_SID_SDMMC3>;
796 iommus = <&smmu TEGRA194_SID_SDMMC4>;
828 iommus = <&smmu TEGRA194_SID_HDA>;
954 iommus = <&smmu TEGRA194_SID_XUSB_DEV>;
987 iommus = <&smmu TEGRA194_SID_XUSB_HOST>;
1316 smmu: iommu@12000000 { label
1317 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"
[all...] |
| tegra186.dtsi | 66 iommus = <&smmu TEGRA186_SID_EQOS>;
640 iommus = <&smmu TEGRA186_SID_SDMMC1>;
670 iommus = <&smmu TEGRA186_SID_SDMMC2>;
695 iommus = <&smmu TEGRA186_SID_SDMMC3>;
725 iommus = <&smmu TEGRA186_SID_SDMMC4>;
756 iommus = <&smmu TEGRA186_SID_HDA>;
887 iommus = <&smmu TEGRA186_SID_XUSB_HOST>;
909 iommus = <&smmu TEGRA186_SID_XUSB_DEV>;
1129 iommus = <&smmu TEGRA186_SID_AFI>;
1130 iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>
1175 smmu: iommu@12000000 { label
[all...] |
| /src/usr.sbin/acpitools/acpidump/ |
| acpi.c | 2097 { NDMAC(SMMU), "SMMUv1 or v2", PRFN(smmuv1v2)},
2199 ACPI_IORT_SMMU *smmu = (ACPI_IORT_SMMU *)node->NodeData; local in function:acpi_print_iort_smmuv1v2
2204 printf("\tBase Address=%016jx\n", (uintmax_t)smmu->BaseAddress);
2205 printf("\tSpan=%016jx\n", (uintmax_t)smmu->Span);
2207 switch (smmu->Model) {
2227 printf("reserved (%u)\n", smmu->Model);
2232 PRINTFLAG(smmu->Flags, DVM_SUPPORTED);
2233 PRINTFLAG(smmu->Flags, COHERENT_WALK);
2238 + smmu->GlobalInterruptOffset);
2246 if (smmu->ContextInterruptCount != 0)
2271 ACPI_IORT_SMMU_V3 *smmu = (ACPI_IORT_SMMU_V3 *)node->NodeData; local in function:acpi_print_iort_smmuv3
[all...] |
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/broadcom/stingray/ |
| stingray.dtsi | 185 smmu: mmu@3000000 { label
563 iommus = <&smmu 0x6000 0x0000>;
594 iommus = <&smmu 0x6002 0x0000>;
604 iommus = <&smmu 0x6003 0x0000>;
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/qcom/ |
| sdm630.dtsi | 606 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
1097 compatible = "qcom,sdm630-smmu-v2",
1098 "qcom,adreno-smmu", "qcom,smmu-v2";
1102 * GX GDSC parent is CX. We need to bring up CX for SMMU
1149 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
2024 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"
[all...] |
| msm8996.dtsi | 1930 compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
1995 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2011 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2031 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2047 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"
[all...] |
| msm8998.dtsi | 900 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
915 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
|
| sdm845-cheza.dtsi | 638 * GPU to update the SMMU pagetables for context switches. Work
639 * around this by dropping the "qcom,adreno-smmu" compat string.
642 compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2";
|
| sc7180.dtsi | 2034 compatible = "qcom,sc7180-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
3250 compatible = "qcom,sc7180-smmu-500", "arm,mmu-500";
|
| sdm845.dtsi | 4453 compatible = "qcom,sdm845-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
4637 compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/freescale/ |
| fsl-lx2160a.dtsi | 1114 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1142 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1170 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1198 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1226 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1254 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1258 smmu: iommu@5000000 { label
1625 iommu-map = <0 &smmu 0 0>;
|
| fsl-ls1088a.dtsi | 564 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
601 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
637 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
651 smmu: iommu@5000000 { label
934 iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */
|
| fsl-ls208xa.dtsi | 753 iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */
870 smmu: iommu@5000000 { label
1086 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1108 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1130 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1152 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
|
| fsl-ls1028a.dtsi | 641 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
668 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
672 smmu: iommu@5000000 { label in label:soc
991 iommu-map = <0 &smmu 0x17 0xe>;
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/marvell/ |
| armada-ap80x.dtsi | 59 smmu: iommu@5000000 { label
60 compatible = "marvell,ap806-smmu-500", "arm,mmu-500";
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/hisilicon/ |
| hip06.dtsi | 325 * have a SMMU translation for MSI. In order to workaround this,
328 * systems. Hence please make sure that the smmu pcie node on
334 compatible = "arm,smmu-v3";
|
| hip07.dtsi | 1156 * have a SMMU translation for MSI. In order to workaround this,
1159 * systems. Hence please make sure that the smmu pcie node on
1165 compatible = "arm,smmu-v3";
1173 compatible = "arm,smmu-v3";
1185 compatible = "arm,smmu-v3";
1197 compatible = "arm,smmu-v3";
1209 compatible = "arm,smmu-v3";
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/broadcom/northstar2/ |
| ns2.dtsi | 298 smmu: mmu@64000000 { label in label:soc
|
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| qcom-sdx55.dtsi | 507 compatible = "qcom,sdx55-smmu-500", "arm,mmu-500";
|
