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    Searched refs:smnDF_CS_UMC_AON0_DramLimitAddress0 (Results 1 - 2 of 2) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/df/
df_3_6_offset.h	77 #define smnDF_CS_UMC_AON0_DramLimitAddress0 0x1c114UL
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_df_v3_6.c	739 xgmi_node_id = RREG32_PCIE(smnDF_CS_UMC_AON0_DramLimitAddress0 +

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