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    Searched refs:smu_tables (Results 1 - 8 of 8) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
amdgpu_vega12_smumgr.c 54 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,
56 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
60 upper_32_bits(priv->smu_tables.entry[table_id].mc_addr)) == 0,
64 lower_32_bits(priv->smu_tables.entry[table_id].mc_addr)) == 0,
76 memcpy(table, priv->smu_tables.entry[table_id].table,
77 priv->smu_tables.entry[table_id].size);
96 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,
98 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
101 memcpy(priv->smu_tables.entry[table_id].table, table,
102 priv->smu_tables.entry[table_id].size)
    [all...]
amdgpu_vega10_smumgr.c 51 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,
53 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
57 upper_32_bits(priv->smu_tables.entry[table_id].mc_addr));
60 lower_32_bits(priv->smu_tables.entry[table_id].mc_addr));
63 priv->smu_tables.entry[table_id].table_id);
68 memcpy(table, priv->smu_tables.entry[table_id].table,
69 priv->smu_tables.entry[table_id].size);
88 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,
90 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
93 memcpy(priv->smu_tables.entry[table_id].table, table
    [all...]
amdgpu_vega20_smumgr.c 176 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,
178 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
183 upper_32_bits(priv->smu_tables.entry[table_id].mc_addr))) == 0,
188 lower_32_bits(priv->smu_tables.entry[table_id].mc_addr))) == 0,
199 memcpy(table, priv->smu_tables.entry[table_id].table,
200 priv->smu_tables.entry[table_id].size);
220 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,
222 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
225 memcpy(priv->smu_tables.entry[table_id].table, table,
226 priv->smu_tables.entry[table_id].size)
    [all...]
amdgpu_smu10_smumgr.c 130 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,
132 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
136 upper_32_bits(priv->smu_tables.entry[table_id].mc_addr));
139 lower_32_bits(priv->smu_tables.entry[table_id].mc_addr));
142 priv->smu_tables.entry[table_id].table_id);
147 memcpy(table, (uint8_t *)priv->smu_tables.entry[table_id].table,
148 priv->smu_tables.entry[table_id].size);
162 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,
164 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
167 memcpy(priv->smu_tables.entry[table_id].table, table
    [all...]
smu10_smumgr.h 48 struct smu_table_array smu_tables; member in struct:smu10_smumgr
vega10_smumgr.h 44 struct smu_table_array smu_tables; member in struct:vega10_smumgr
vega12_smumgr.h 45 struct smu_table_array smu_tables; member in struct:vega12_smumgr
vega20_smumgr.h 44 struct smu_table_array smu_tables; member in struct:vega20_smumgr

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