| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/ |
| amdgpu_smu_v12_0.c | 383 uint32_t mclk_mask, soc_mask; local in function:smu_v12_0_get_dpm_ultimate_freq
389 &soc_mask);
413 ret = smu_get_dpm_clk_limited(smu, clk_type, soc_mask, max);
|
| amdgpu_renoir_ppt.c | 550 uint32_t *soc_mask)
567 if(soc_mask)
568 *soc_mask = NUM_SOCCLK_DPM_LEVELS - 1;
726 uint32_t sclk_mask, mclk_mask, soc_mask; local in function:renoir_set_performance_level
744 &soc_mask);
749 smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask, false);
|
| smu_internal.h | 142 #define smu_get_profiling_clk_mask(smu, level, sclk_mask, mclk_mask, soc_mask) \
143 ((smu)->ppt_funcs->get_profiling_clk_mask ? (smu)->ppt_funcs->get_profiling_clk_mask((smu), (level), (sclk_mask), (mclk_mask), (soc_mask)) : 0)
|
| amdgpu_navi10_ppt.c | 1421 uint32_t *soc_mask)
1447 if(soc_mask) {
1451 *soc_mask = level_count - 1;
1768 uint32_t sclk_mask, mclk_mask, soc_mask; local in function:navi10_set_performance_level
1788 &soc_mask);
1793 smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask, false);
|
| amdgpu_smu_v11_0.c | 1911 uint32_t sclk_mask, mclk_mask, soc_mask; local in function:smu_v11_0_set_performance_level
1930 &soc_mask);
1935 smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask, false);
|
| amdgpu_arcturus_ppt.c | 1246 uint32_t *soc_mask)
1263 *soc_mask = 0;
1270 *soc_mask = ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL;
1280 *soc_mask = soc_dpm_table->count - 1;
|
| amdgpu_vega20_ppt.c | 1977 uint32_t *soc_mask)
1993 *soc_mask = 0;
2000 *soc_mask = VEGA20_UMD_PSTATE_SOCCLK_LEVEL;
2010 *soc_mask = soc_dpm_table->count - 1;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/ |
| amdgpu_vega12_hwmgr.c | 1588 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask)
1597 *soc_mask = 0;
1604 *soc_mask = VEGA12_UMD_PSTATE_SOCCLK_LEVEL;
1614 *soc_mask = soc_dpm_table->count - 1;
1644 uint32_t soc_mask = 0; local in function:vega12_dpm_force_dpm_level
1660 ret = vega12_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
|
| amdgpu_vega20_hwmgr.c | 2484 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask)
2493 *soc_mask = 0;
2500 *soc_mask = VEGA20_UMD_PSTATE_SOCCLK_LEVEL;
2510 *soc_mask = soc_dpm_table->count - 1;
2683 uint32_t sclk_mask, mclk_mask, soc_mask; local in function:vega20_dpm_force_dpm_level
2702 ret = vega20_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
2707 vega20_force_clock_level(hwmgr, PP_SOCCLK, 1 << soc_mask);
|
| amdgpu_vega10_hwmgr.c | 4086 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask)
4095 *soc_mask = VEGA10_UMD_PSTATE_SOCCLK_LEVEL;
4113 *soc_mask = table_info->vdd_dep_on_socclk->count - 1;
4207 uint32_t soc_mask = 0; local in function:vega10_dpm_force_dpm_level
4210 vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
4226 ret = vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/ |
| amdgpu_smu.h | 467 uint32_t *soc_mask);
|
