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    Searched refs:socclk (Results 1 - 9 of 9) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/
dcn_calcs.h 129 float socclk; member in struct:dcn_bw_internal_vars
566 float socclk; /*MHz*/ member in struct:dcn_soc_bounding_box
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/
amdgpu_dcn_calcs.c 118 .socclk = 208, /*MHz*/
486 input.clks_cfg.socclk_mhz = v->socclk;
771 v->socclk = dc->dcn_soc->socclk;
1516 socclk_khz = dc->dcn_soc->socclk * 1000;
1524 /* SOCCLK does not affect anytihng but writeback for DCN so for now we dont
1587 "socclk: %f kHz\n"
1621 dc->dcn_soc->socclk * 1000,
amdgpu_dcn_calc_auto.c 1342 v->writeback_dram_clock_change_watermark = v->dram_clock_change_latency + v->write_back_latency + v->writeback_chunk_size * 1024.0 / 32.0 / v->socclk;
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/
amdgpu_smu_v11_0.c 536 smu->smu_table.boot_values.socclk = 0;
551 smu->smu_table.boot_values.socclk = 0;
585 smu->smu_table.boot_values.socclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
993 max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
1015 pr_err("[%s] failed to get max SOCCLK from SMC!",
amdgpu_arcturus_ppt.c 140 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
431 /* socclk */
437 pr_err("[%s] failed to get socclk dpm levels!\n", __func__);
442 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
690 pr_err("Attempt to get current socclk Failed!");
697 pr_err("Attempt to get socclk levels Failed!");
789 pr_err("Failed to set soft %s socclk !\n",
844 * support mclk/socclk/fclk softmin/softmax settings
1091 * But this is available for gfxclk/uclk/socclk.
amdgpu_smu.c 301 clock_limit = smu->smu_table.boot_values.socclk;
amdgpu_vega20_ppt.c 162 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
731 /* socclk */
738 pr_err("[SetupDefaultDpmTable] failed to get socclk dpm levels!");
743 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
1016 pr_err("Attempt to get current socclk Failed!");
1023 pr_err("Attempt to get socclk levels Failed!");
1242 pr_err("Failed to set soft %s socclk !\n",
1840 "SOCCLK",
1918 case 1: /* Socclk */
2201 /* socclk */
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  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
amdgpu_smu.h 216 uint32_t socclk; member in struct:smu_bios_boot_up_values
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
amdgpu_vega10_hwmgr.c 524 uint16_t virtual_voltage_id, int32_t *socclk)
546 *socclk = table_info->vdd_dep_on_socclk->entries[entry_id].clk;
1327 "SOCCLK dependency table is missing. This table is mandatory",
1330 "SOCCLK dependency table is empty. This table is mandatory",
1618 * @brief Populates single SMC SOCCLK structure using the provided clock.
1622 * @param current_socclk_level - location in PPTable for the SMC SOCCLK structure.

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