| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn20/ |
| amdgpu_dcn20_clk_mgr.c | 215 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz)) {
216 clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz;
218 pp_smu->set_hard_min_socclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.socclk_khz / 1000);
299 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr->clks.socclk_khz)) {
300 clk_mgr->clks.socclk_khz = new_clocks->socclk_khz;
410 else if (a->socclk_khz != b->socclk_khz
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/ |
| amdgpu_dc_debug.c | 356 "dcfclk_deep_sleep_khz:%d fclk_khz:%d socclk_khz:%d\n",
362 context->bw_ctx.bw.dcn.clk.socclk_khz);
364 "dcfclk_deep_sleep_khz:%d fclk_khz:%d socclk_khz:%d\n",
370 context->bw_ctx.bw.dcn.clk.socclk_khz);
|
| amdgpu_dc.c | 2698 info->socClock = (unsigned int)state->bw_ctx.bw.dcn.clk.socclk_khz;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/ |
| dc.h | 281 int socclk_khz; member in struct:dc_clocks
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_hw_sequencer_debug.c | 485 dc->current_state->bw_ctx.bw.dcn.clk.socclk_khz);
|
| amdgpu_dcn10_hw_sequencer.c | 452 "dppclk_khz:%d max_supported_dppclk_khz:%d fclk_khz:%d socclk_khz:%d\n\n",
459 dc->current_state->bw_ctx.bw.dcn.clk.socclk_khz);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/ |
| amdgpu_dcn_calcs.c | 1505 volatile int min_fclk_khz, min_dcfclk_khz, socclk_khz; local in function:dcn_bw_notify_pplib_of_wm_ranges
1516 socclk_khz = dc->dcn_soc->socclk * 1000;
1535 ranges.writer_wm_sets[0].min_fill_clk_mhz = socclk_khz / 1000;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_resource.c | 2789 context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000;
|
