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    Searched refs:soculvphasesheddingmask (Results 1 - 6 of 6) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
ppatomfwctrl.h 173 uint8_t soculvphasesheddingmask; member in struct:pp_atomfwctrl_smc_dpm_parameters
amdgpu_vega12_processpptables.c 140 ppsmc_pptable->SocUlvPhaseSheddingMask = smc_dpm_table.soculvphasesheddingmask;
amdgpu_ppatomfwctrl.c 664 param->soculvphasesheddingmask = info->soculvphasesheddingmask;
amdgpu_vega20_processpptables.c 566 pr_info("SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
741 ppsmc_pptable->SocUlvPhaseSheddingMask = smc_dpm_table->soculvphasesheddingmask;
  /src/sys/external/bsd/drm2/dist/drm/amd/include/
atomfirmware.h 1434 uint8_t soculvphasesheddingmask; member in struct:atom_smc_dpm_info_v4_1
1522 uint8_t soculvphasesheddingmask; member in struct:atom_smc_dpm_info_v4_3
1600 uint8_t soculvphasesheddingmask; member in struct:atom_smc_dpm_info_v4_4
1727 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/
amdgpu_vega20_ppt.c 508 smc_pptable->SocUlvPhaseSheddingMask = smc_dpm_table->soculvphasesheddingmask;

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