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    Searched refs:source_scan (Results 1 - 10 of 10) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/
amdgpu_dcn_calc_auto.c 50 if (v->source_scan[k] == dcn_bw_hor) {
60 if (v->source_scan[k] == dcn_bw_hor) {
145 if ((v->source_surface_mode[k] == dcn_bw_sw_linear && v->source_scan[k] != dcn_bw_hor) || ((v->source_surface_mode[k] == dcn_bw_sw_4_kb_d || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x || v->source_surface_mode[k] == dcn_bw_sw_var_d || v->source_surface_mode[k] == dcn_bw_sw_var_d_x) && v->source_pixel_format[k] != dcn_bw_rgb_sub_64)) {
152 if (v->source_scan[k] == dcn_bw_hor) {
185 if (v->pte_enable == dcn_bw_yes && v->source_scan[k] != dcn_bw_hor && (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d_x)) {
188 else if (v->pte_enable == dcn_bw_yes && v->source_scan[k] == dcn_bw_hor && (v->source_pixel_format[k] == dcn_bw_rgb_sub_64 || v->source_pixel_format[k] == dcn_bw_rgb_sub_32) && (v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x)) {
379 if (v->source_scan[k] == dcn_bw_hor) {
388 if (v->source_surface_mode[k] == dcn_bw_sw_linear || (v->source_pixel_format[k] == dcn_bw_rgb_sub_64 && (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_var_s || v->source_surface_mode[k] == dcn_bw_sw_var_s_x) && v->source_scan[k] == dcn_bw_hor)) {
401 else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8 && v->source_scan[k] == dcn_bw_hor) {
410 else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10 && v->source_scan[k] == dcn_bw_hor)
    [all...]
amdgpu_dcn_calcs.c 335 input->src.source_scan = dm_horz;
350 input->src.source_scan = dm_horz;
354 input->src.source_scan = dm_vert;
913 v->source_scan[input_idx] = dcn_bw_hor;
999 v->source_scan[input_idx] = (pipe->plane_state->rotation % 2) ? dcn_bw_vert : dcn_bw_hor;
1060 if (v->source_scan[k] == dcn_bw_hor)
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn21/
amdgpu_display_rq_dlg_calc_21.c 233 bool surf_vert = (pipe_src_param.source_scan == dm_vert);
319 unsigned int source_scan,
324 bool surf_vert = (source_scan == dm_vert);
712 access_dir = (pipe_param.src.source_scan == dm_vert); // vp access direction: horizontal or vertical accessed
761 pipe_param.src.source_scan,
1019 access_dir = (src->source_scan == dm_vert); // vp access direction: horizontal or vertical accessed
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/
display_mode_structs.h 229 int source_scan; member in struct:_vcs_dpi_display_pipe_source_params_st
amdgpu_dml1_display_rq_dlg_calc.c 290 bool surf_vert = (pipe_src_param.source_scan == dm_vert);
378 int source_scan,
382 bool surf_vert = (source_scan == dm_vert);
636 surf_vert = (pipe_src_param.source_scan == dm_vert);
923 pipe_src_param.source_scan,
1191 access_dir = (e2e_pipe_param.pipe.src.source_scan == dm_vert); /* vp access direction: horizontal or vertical accessed */
amdgpu_display_mode_vba.c 390 (enum scan_direction_class) (src->source_scan);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn20/
amdgpu_display_rq_dlg_calc_20.c 251 bool surf_vert = (pipe_src_param.source_scan == dm_vert);
332 unsigned int source_scan,
336 bool surf_vert = (source_scan == dm_vert);
721 pipe_src_param.source_scan,
967 access_dir = (src->source_scan == dm_vert); // vp access direction: horizontal or vertical accessed
amdgpu_display_rq_dlg_calc_20v2.c 251 bool surf_vert = (pipe_src_param.source_scan == dm_vert);
332 unsigned int source_scan,
336 bool surf_vert = (source_scan == dm_vert);
721 pipe_src_param.source_scan,
968 access_dir = (src->source_scan == dm_vert); // vp access direction: horizontal or vertical accessed
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/
dcn_calcs.h 186 enum dcn_bw_defs source_scan[number_of_planes_minus_one + 1]; member in struct:dcn_bw_internal_vars
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_resource.c 2070 pipes[pipe_cnt].pipe.src.source_scan = dm_horz;
2108 pipes[pipe_cnt].pipe.src.source_scan = pln->rotation == ROTATION_ANGLE_90

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