| /src/sys/dev/ata/ |
| sata_subr.c | 50 * the port's SStatus register.
53 sata_speed(uint32_t sstatus)
74 return (sata_speedtab[(sstatus & SStatus_SPD_mask) >>
85 uint32_t scontrol, sstatus; local in function:sata_reset_interface
106 sstatus = bus_space_read_4(sata_t, sstatus_r, 0);
107 if ((sstatus & SStatus_DET_mask) == SStatus_DET_DEV)
115 if ((sstatus & SStatus_DET_mask) == SStatus_DET_DEV_NE) {
118 sstatus = bus_space_read_4(sata_t, sstatus_r, 0);
119 if ((sstatus & SStatus_DET_mask) == SStatus_DET_DEV)
124 sata_interpret_det(chp, sstatus);
[all...] |
| satapmp_subr.c | 187 uint32_t scontrol, sstatus; local in function:satapmp_reset_device_port
206 if (satapmp_read(chp, port, PMP_PSCR_SStatus, &sstatus,
209 if ((sstatus & SStatus_DET_mask) == SStatus_DET_DEV)
214 switch (sstatus & SStatus_DET_mask) {
229 device_xname(chp->atabus), port, sata_speed(sstatus));
232 aprint_error("%s PMP port %d: unknown SStatus: 0x%08x\n",
233 device_xname(chp->atabus), port, sstatus);
235 return(sstatus & SStatus_DET_mask);
|
| /src/sys/arch/evbmips/sbmips/ |
| sb1250_icu.c | 311 uint64_t sstatus = ints_for_ipl[ipl]; local in function:sb1250_cpu_intr
312 sstatus &= READ_REG(imr_base + R_IMR_INTERRUPT_SOURCE_STATUS);
313 while (sstatus != 0) {
316 __asm("dclz %0,%1" : "=r"(n) : "r"(sstatus));
318 u_int n = (sstatus >> 32)
319 ? 0 + __builtin_clz(sstatus >> 32)
320 : 32 + __builtin_clz((uint32_t)sstatus);
323 KASSERT(sstatus & (1ULL << j));
324 sstatus ^= (1ULL << j);
|
| /src/sys/arch/sbmips/sbmips/ |
| sb1250_icu.c | 311 uint64_t sstatus = ints_for_ipl[ipl]; local in function:sb1250_cpu_intr
312 sstatus &= READ_REG(imr_base + R_IMR_INTERRUPT_SOURCE_STATUS);
313 while (sstatus != 0) {
316 __asm("dclz %0,%1" : "=r"(n) : "r"(sstatus));
318 u_int n = (sstatus >> 32)
319 ? 0 + __builtin_clz(sstatus >> 32)
320 : 32 + __builtin_clz((uint32_t)sstatus);
323 KASSERT(sstatus & (1ULL << j));
324 sstatus ^= (1ULL << j);
|
| /src/sys/arch/riscv/riscv/ |
| cpu_switch.S | 60 csrrci t0, sstatus, SR_SIE // # disable interrupts
90 csrw sstatus, t0 // enable interrupts
171 csrr t4, sstatus // get status register (for intr state)
177 csrrci t0, sstatus, SR_SIE // disable interrupts
193 csrw sstatus, t0 // reenable interrupts
195 csrrci t0, sstatus, SR_SIE // disable interrupts
202 csrw sstatus, t0 // reenable interrupts
303 csrr a2, sstatus // get status
360 csrw sstatus, t1 // restore sstatus (needs to have SIE=0
[all...] |
| copy.S | 71 csrs sstatus, t1
77 csrc sstatus, t1
|
| spl.S | 97 csrsi sstatus, SR_SIE // enable interrupts
|
| locore.S | 86 csrc sstatus, s0 // disable FP
495 csrsi sstatus, SR_SIE // enable interrupts
|
| /src/sys/dev/pci/ |
| satalink.c | 497 /* We can use SControl and SStatus to probe for drives. */
736 /* We can use SControl and SStatus to probe for drives. */
785 uint32_t scontrol, sstatus; local in function:sii3112_drv_probe
815 sstatus = BA5_READ_4(sc, chp->ch_channel, ba5_SStatus);
818 "port %d: SStatus=0x%08x, SControl=0x%08x\n",
819 chp->ch_channel, sstatus,
822 switch (sstatus & SStatus_DET_mask) {
882 sata_speed(sstatus));
887 "port %d: unknown SStatus: 0x%08x\n",
888 chp->ch_channel, sstatus);
[all...] |
| /src/usr.sbin/rpc.lockd/ |
| lockd_lock.c | 436 int sstatus; local in function:sigchild_handler
441 pid = wait4(-1, &sstatus, WNOHANG, NULL);
468 if (!WIFEXITED(sstatus) || WEXITSTATUS(sstatus) != 0) {
|
| /src/sys/arch/riscv/include/ |
| sysreg.h | 166 RISCVREG_READ_SET_CLEAR_INLINE(sstatus) // supervisor status register
235 // U-mode sstatus values
|
