| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/ |
| amdgpu_dc_link_hwss.c | 121 pipes[i].stream_res.pix_clk_params.requested_pix_clk_100hz =
125 &pipes[i].stream_res.pix_clk_params,
323 pipes[i].stream_res.stream_enc != NULL &&
327 pipes[i].stream_res.stream_enc->funcs->dp_blank(
328 pipes[i].stream_res.stream_enc);
337 if ((&pipes[i])->stream_res.audio && !link->dc->debug.az_endpoint_mute_only)
338 (&pipes[i])->stream_res.audio->funcs->az_disable((&pipes[i])->stream_res.audio);
360 if (pipes[i].stream_res.audio) {
363 pipes[i].stream_res.audio->funcs->az_enable
[all...] |
| amdgpu_dc_resource.c | 1244 split_pipe->stream_res.tg = pool->timing_generators[i];
1248 split_pipe->stream_res.opp = pool->opps[i];
1319 free_pipe->stream_res.tg = tail_pipe->stream_res.tg;
1320 free_pipe->stream_res.abm = tail_pipe->stream_res.abm;
1321 free_pipe->stream_res.opp = tail_pipe->stream_res.opp;
1322 free_pipe->stream_res.stream_enc = tail_pipe->stream_res.stream_enc
[all...] |
| amdgpu_dc.c | 294 if (pipe->stream == stream && pipe->stream_res.tg) {
322 if (pipe->stream == stream && pipe->stream_res.stream_enc) {
376 tg = pipe->stream_res.tg;
410 tg = pipe->stream_res.tg;
429 pipe_ctx->stream_res.opp->dyn_expansion = option;
430 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
431 pipe_ctx->stream_res.opp,
474 pipes->stream_res.opp->funcs->
475 opp_program_bit_depth_reduction(pipes->stream_res.opp, ¶ms);
510 pipes->stream_res.opp->inst)
[all...] |
| amdgpu_dc_link.c | 1518 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk =
2092 eng_id = pipe_ctx->stream_res.stream_enc->id;
2367 res_ctx.pipe_ctx[i].stream_res.tg->inst +
2531 pipe_ctx[i].stream_res.tg->inst + 1;
2719 struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
2740 link, pipe_ctx->stream_res.stream_enc, &proposed_table);
2802 struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
2830 link, pipe_ctx->stream_res.stream_enc, &proposed_table);
2912 pipe_ctx->stream_res.stream_enc->id, true);
2929 config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst
[all...] |
| amdgpu_dc_debug.c | 331 pipe_ctx->stream_res.tg->funcs->get_position(pipe_ctx->stream_res.tg, &position);
342 pipe_ctx->stream_res.tg->inst,
|
| amdgpu_dc_link_dp.c | 1536 pipe_ctx->stream_res.stream_enc->id, true);
3634 struct output_pixel_processor *opp = pipe_ctx->stream_res.opp;
3681 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
3682 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
3714 struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp;
3747 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
3748 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
3760 struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp
[all...] |
| amdgpu_dc_stream.c | 516 struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg;
575 struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_hwseq.c | 92 * Groups in stream_res are stored as +1 from HW registers, i.e.
93 * gsl_0 <=> pipe_ctx->stream_res.gsl_group == 1
110 if (pipe_ctx->stream_res.gsl_group > 0)
115 pipe_ctx->stream_res.gsl_group = group_idx;
137 group_idx = pipe_ctx->stream_res.gsl_group;
141 pipe_ctx->stream_res.gsl_group = 0;
165 if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL &&
166 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) {
167 pipe_ctx->stream_res.tg->funcs->set_gsl(
168 pipe_ctx->stream_res.tg
941 struct stream_resource *stream_res = &pipe_ctx->stream_res; local in function:dcn20_blank_pixel_data
[all...] |
| amdgpu_dcn20_resource.c | 1458 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
1491 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
1495 &pipe_ctx->stream_res.pix_clk_params,
1596 if (pipe_ctx->stream_res.dsc)
1599 acquire_dsc(&dc_ctx->res_ctx, pool, &pipe_ctx->stream_res.dsc, i);
1602 if (!pipe_ctx->stream_res.dsc) {
1624 if (pipe_ctx->stream_res.dsc)
1625 release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc);
1743 next_odm_pipe->stream_res.dsc = NULL;
1788 next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx]
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/ |
| amdgpu_dce110_hw_sequencer.c | 638 if (pipe_ctx->stream_res.stream_enc == NULL)
648 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(
649 pipe_ctx->stream_res.stream_enc,
650 &pipe_ctx->stream_res.encoder_info_frame);
652 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(
653 pipe_ctx->stream_res.stream_enc,
654 &pipe_ctx->stream_res.encoder_info_frame);
667 struct timing_generator *tg = pipe_ctx->stream_res.tg;
674 pipe_ctx->stream_res.stream_enc->id, true);
693 if (pipe_ctx->stream_res.audio != NULL)
[all...] |
| amdgpu_dce110_resource.c | 873 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
897 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
900 &pipe_ctx->stream_res.pix_clk_params,
1113 pipe_ctx->stream_res.tg = pool->timing_generators[underlay_idx];
1117 pipe_ctx->stream_res.opp = pool->opps[underlay_idx];
1128 pipe_ctx->stream_res.tg->inst,
1136 pipe_ctx->stream_res.tg->funcs->program_timing(pipe_ctx->stream_res.tg,
1145 pipe_ctx->stream_res.tg->funcs->enable_advanced_request(
1146 pipe_ctx->stream_res.tg
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| amdgpu_dce_hwseq.c | 61 if (lock && pipe->stream_res.tg->funcs->is_blanked &&
62 pipe->stream_res.tg->funcs->is_blanked(pipe->stream_res.tg))
65 val = REG_GET_4(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst],
76 REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val,
81 REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val,
87 uint32_t value = REG_READ(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst]);
88 REG_WRITE(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst], value);
|
| dmub_psr.c | 123 !&pipe_ctx->stream_res)
154 if (pipe_ctx->stream_res.opp)
155 copy_settings_data->opp_inst = pipe_ctx->stream_res.opp->inst;
158 if (pipe_ctx->stream_res.tg)
159 copy_settings_data->otg_inst = pipe_ctx->stream_res.tg->inst;
|
| dce_clk_mgr.c | 204 if (pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10 > max_pix_clk)
205 max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10;
211 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk > max_pix_clk)
212 max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_sym_clk;
525 cfg->pipe_idx = pipe_ctx->stream_res.tg->inst;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_hw_sequencer.c | 100 tg = pipe_ctx->stream_res.tg;
469 struct timing_generator *tg = pipe_ctx->stream_res.tg;
798 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true);
802 &pipe_ctx->stream_res.pix_clk_params,
808 pipe_ctx->stream_res.tg->funcs->program_timing(
809 pipe_ctx->stream_res.tg,
822 inst_offset = reg_offsets[pipe_ctx->stream_res.tg->inst].fmt;
824 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
825 pipe_ctx->stream_res.opp
2370 struct stream_resource *stream_res = &pipe_ctx->stream_res; local in function:dcn10_blank_pixel_data
[all...] |
| amdgpu_dcn10_resource.c | 1037 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
1067 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
1071 &pipe_ctx->stream_res.pix_clk_params,
1150 idle_pipe->stream_res.tg = head_pipe->stream_res.tg;
1151 idle_pipe->stream_res.abm = head_pipe->stream_res.abm;
1152 idle_pipe->stream_res.opp = head_pipe->stream_res.opp;
|
| amdgpu_dcn10_hw_sequencer_debug.c | 437 pix_clk = dc->current_state->res_ctx.pipe_ctx[i].stream_res.pix_clk_params.requested_pix_clk_100hz / 10;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce100/ |
| amdgpu_dce_clk_mgr.c | 185 if (pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10 > max_pix_clk)
186 max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10;
192 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk > max_pix_clk)
193 max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_sym_clk;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce110/ |
| amdgpu_dce110_clk_mgr.c | 153 cfg->pipe_idx = pipe_ctx->stream_res.tg->inst;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/ |
| core_types.h | 283 struct stream_resource stream_res; member in struct:pipe_ctx
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dce110/ |
| amdgpu_irq_service_dce110.c | 220 dc->current_state->res_ctx.pipe_ctx[pipe_offset].stream_res.tg;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/ |
| amdgpu_dcn_calcs.c | 1250 /* Clear plane_res and stream_res */
1252 memset(&hsplit_pipe->stream_res, 0, sizeof(hsplit_pipe->stream_res));
|
