| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_resource.c | 1668 unsigned int *sw_mode)
1672 *sw_mode = dm_sw_linear;
1675 *sw_mode = dm_sw_4kb_s;
1678 *sw_mode = dm_sw_4kb_s_x;
1681 *sw_mode = dm_sw_4kb_d;
1684 *sw_mode = dm_sw_4kb_d_x;
1687 *sw_mode = dm_sw_64kb_s;
1690 *sw_mode = dm_sw_64kb_s_x;
1693 *sw_mode = dm_sw_64kb_s_t;
1696 *sw_mode = dm_sw_64kb_d
[all...] |
| amdgpu_dcn20_hubp.c | 310 * SW_MODE
323 SW_MODE, info->gfx9.swizzle,
1202 SW_MODE, &s->sw_mode);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_uvd_v4_2.c | 55 bool sw_mode);
608 bool sw_mode)
620 if (sw_mode) {
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/ |
| display_mode_structs.h | 230 int sw_mode; member in struct:_vcs_dpi_display_pipe_source_params_st
|
| amdgpu_dml1_display_rq_dlg_calc.c | 289 bool surf_linear = (pipe_src_param.sw_mode == dm_sw_linear);
635 surf_linear = (pipe_src_param.sw_mode == dm_sw_linear);
672 if (pipe_src_param.sw_mode != dm_sw_linear)
921 pipe_src_param.sw_mode,
|
| amdgpu_display_mode_vba.c | 440 (enum dm_swizzle_mode) (src->sw_mode);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_hw_sequencer_debug.c | 127 chars_printed = snprintf_count(pBuf, remaining_buffer, "instance,format,addr_hi,width,height,rotation,mirror,sw_mode,dcc_en,blank_en,ttu_dis,underflow,"
131 chars_printed = snprintf_count(pBuf, remaining_buffer, "instance,format,addr_hi,addr_lo,width,height,rotation,mirror,sw_mode,dcc_en,blank_en,ttu_dis,underflow,"
156 s->sw_mode,
176 s->sw_mode,
|
| dcn10_hubp.h | 271 HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, SW_MODE, mask_sh),\
466 type SW_MODE;\
672 uint32_t sw_mode; member in struct:dcn_hubp_state
|
| amdgpu_dcn10_hubp.c | 162 SW_MODE, info->gfx9.swizzle,
1010 SW_MODE, &s->sw_mode);
|
| amdgpu_dcn10_hw_sequencer.c | 166 "HUBP: format addr_hi width height rot mir sw_mode dcc_en blank_en clock_en ttu_dis underflow min_ttu_vblank qos_low_wm qos_high_wm\n");
182 s->sw_mode,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/ |
| dcn_calcs.h | 637 enum source_macro_tile_size swizzle_mode_to_macro_tile_size(enum swizzle_mode_values sw_mode);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/ |
| amdgpu_dcn_calcs.c | 167 static enum dcn_bw_defs tl_sw_mode_to_bw_defs(enum swizzle_mode_values sw_mode)
169 switch (sw_mode) {
258 enum source_macro_tile_size swizzle_mode_to_macro_tile_size(enum swizzle_mode_values sw_mode)
260 switch (sw_mode) {
336 input->src.sw_mode = pipe->plane_state->tiling_info.gfx9.swizzle;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn20/ |
| amdgpu_display_rq_dlg_calc_20.c | 250 bool surf_linear = (pipe_src_param.sw_mode == dm_sw_linear);
719 pipe_src_param.sw_mode,
|
| amdgpu_display_rq_dlg_calc_20v2.c | 250 bool surf_linear = (pipe_src_param.sw_mode == dm_sw_linear);
719 pipe_src_param.sw_mode,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn21/ |
| amdgpu_display_rq_dlg_calc_21.c | 232 bool surf_linear = (pipe_src_param.sw_mode == dm_sw_linear);
759 pipe_param.src.sw_mode,
|
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_si.c | 5179 bool sw_mode)
5187 if (sw_mode) {
|
