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    Searched refs:swath_height (Results 1 - 11 of 11) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/
amdgpu_dcn21_hubp.c 147 SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height,
155 SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height,
383 SWATH_HEIGHT, &rq_regs.rq_regs_l.swath_height,
391 SWATH_HEIGHT_C, &rq_regs.rq_regs_c.swath_height,
428 if (rq_regs.rq_regs_l.swath_height != dml_rq_regs->rq_regs_l.swath_height)
429 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:SWATH_HEIGHT - Expected: %u Actual: %u\n",
430 dml_rq_regs->rq_regs_l.swath_height, rq_regs.rq_regs_l.swath_height)
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/
amdgpu_dml1_display_rq_dlg_calc.c 137 unsigned int swath_height,
144 vratio_pre = (max_num_sw * swath_height + max_partial_sw) / l_sw;
146 if (swath_height > 4) {
147 double tmp0 = (max_num_sw * swath_height) / (l_sw - (prefill - 3.0) / 2.0);
155 DTRACE("DLG: %s: swath_height = %0d", __func__, swath_height);
179 unsigned int swath_height,
185 DTRACE("DLG: %s: swath_height = %0d", __func__, swath_height);
190 *max_num_sw = (unsigned int) (dml_ceil((prefill - 1.0) / (double) swath_height, 1) + 1.0); /* prefill has to be >= 1 *
    [all...]
amdgpu_display_rq_dlg_helpers.c 78 "DML_RQ_DLG_CALC: swath_height = %0d\n",
79 rq_dlg_param.swath_height);
176 dml_print("DML_RQ_DLG_CALC: swath_height = 0x%0x\n", rq_regs.swath_height);
display_mode_structs.h 382 unsigned int swath_height; member in struct:_vcs_dpi_display_data_rq_dlg_params_st
501 unsigned int swath_height; member in struct:_vcs_dpi_display_data_rq_regs_st
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_hubp.c 217 SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height,
226 SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height,
1239 SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height,
1249 SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height,
1282 SWATH_HEIGHT, &rq_regs.rq_regs_l.swath_height,
1291 SWATH_HEIGHT_C, &rq_regs.rq_regs_c.swath_height,
1328 if (rq_regs.rq_regs_l.swath_height != dml_rq_regs->rq_regs_l.swath_height
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn20/
amdgpu_display_rq_dlg_calc_20.c 41 // rq_param - values that can be used to setup RQ (e.g. swath_height, plane1_addr, etc.)
212 rq_regs->rq_regs_l.swath_height = dml_log2(rq_param.dlg.rq_l.swath_height);
213 rq_regs->rq_regs_c.swath_height = dml_log2(rq_param.dlg.rq_c.swath_height);
308 rq_param->dlg.rq_l.swath_height = 1 << log2_swath_height_l;
309 rq_param->dlg.rq_c.swath_height = 1 << log2_swath_height_c;
990 // unsigned int swath_height_l = rq_dlg_param.rq_l.swath_height;
997 // unsigned int swath_height_c = rq_dlg_param.rq_c.swath_height;
amdgpu_display_rq_dlg_calc_20v2.c 41 // rq_param - values that can be used to setup RQ (e.g. swath_height, plane1_addr, etc.)
212 rq_regs->rq_regs_l.swath_height = dml_log2(rq_param.dlg.rq_l.swath_height);
213 rq_regs->rq_regs_c.swath_height = dml_log2(rq_param.dlg.rq_c.swath_height);
308 rq_param->dlg.rq_l.swath_height = 1 << log2_swath_height_l;
309 rq_param->dlg.rq_c.swath_height = 1 << log2_swath_height_c;
991 // unsigned int swath_height_l = rq_dlg_param.rq_l.swath_height;
998 // unsigned int swath_height_c = rq_dlg_param.rq_c.swath_height;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn21/
amdgpu_display_rq_dlg_calc_21.c 192 rq_regs->rq_regs_l.swath_height = dml_log2(rq_param.dlg.rq_l.swath_height);
193 rq_regs->rq_regs_c.swath_height = dml_log2(rq_param.dlg.rq_c.swath_height);
292 rq_param->dlg.rq_l.swath_height = 1 << log2_swath_height_l;
293 rq_param->dlg.rq_c.swath_height = 1 << log2_swath_height_c;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_hw_sequencer_debug.c 221 rq_regs->rq_regs_l.mpte_group_size, rq_regs->rq_regs_l.swath_height,
225 rq_regs->rq_regs_c.swath_height, rq_regs->rq_regs_c.pte_row_height_linear);
amdgpu_dcn10_hubp.c 565 SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height,
574 SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height,
1047 SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height,
1057 SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height,
amdgpu_dcn10_hw_sequencer.c 209 rq_regs->rq_regs_l.mpte_group_size, rq_regs->rq_regs_l.swath_height,
213 rq_regs->rq_regs_c.swath_height, rq_regs->rq_regs_c.pte_row_height_linear);
1797 "swath_height: %d \n"
1807 pipe_ctx->rq_regs.rq_regs_l.swath_height,

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