| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/ |
| dchubbub.h | 123 enum swizzle_mode_values swizzle,
|
| /src/sys/external/bsd/drm2/dist/drm/i915/gem/selftests/ |
| i915_gem_mman.c | 30 unsigned int swizzle; member in struct:tile
68 switch (tile->swizzle) {
346 tile.swizzle = I915_BIT_6_SWIZZLE_NONE;
371 tile.swizzle = i915->ggtt.bit_6_swizzle_x;
374 tile.swizzle = i915->ggtt.bit_6_swizzle_y;
378 GEM_BUG_ON(tile.swizzle == I915_BIT_6_SWIZZLE_UNKNOWN);
379 if (tile.swizzle == I915_BIT_6_SWIZZLE_9_17 ||
380 tile.swizzle == I915_BIT_6_SWIZZLE_9_10_17)
487 tile.swizzle = I915_BIT_6_SWIZZLE_NONE;
491 tile.swizzle = i915->ggtt.bit_6_swizzle_x
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| dcn20_hubbub.h | 96 enum swizzle_mode_values swizzle,
|
| amdgpu_dcn20_hubbub.c | 62 enum swizzle_mode_values swizzle,
71 switch (swizzle) {
|
| amdgpu_dcn20_resource.c | 1667 enum swizzle_mode_values swizzle,
1670 switch (swizzle) {
2163 swizzle_mode_to_macro_tile_size(pln->tiling_info.gfx9.swizzle);
2164 swizzle_to_dml_params(pln->tiling_info.gfx9.swizzle,
3042 enum swizzle_mode_values swizzle = DC_SW_LINEAR; local in function:dcn20_get_default_swizzle_mode
3045 swizzle = DC_SW_64KB_D;
3047 swizzle = DC_SW_64KB_S;
3049 plane_state->tiling_info.gfx9.swizzle = swizzle;
|
| amdgpu_dcn20_hubp.c | 323 SW_MODE, info->gfx9.swizzle,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/ |
| amdgpu_dc_debug.c | 174 SURFACE_TRACE("plane_state->tiling_info.gfx9.swizzle = %d;\n",
175 plane_state->tiling_info.gfx9.swizzle);
260 SURFACE_TRACE("surface->tiling_info.gfx9.swizzle = %d;\n",
261 update->plane_info->tiling_info.gfx9.swizzle);
|
| amdgpu_dc.c | 1570 if (u->plane_info->tiling_info.gfx9.swizzle != DC_SW_LINEAR) {
|
| amdgpu_dc_resource.c | 2118 pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) {
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_resource.c | 1248 enum swizzle_mode_values swizzle = DC_SW_LINEAR; local in function:dcn10_get_default_swizzle_mode
1251 swizzle = DC_SW_64KB_D;
1253 swizzle = DC_SW_64KB_S;
1255 plane_state->tiling_info.gfx9.swizzle = swizzle;
|
| amdgpu_dcn10_hubbub.c | 729 enum swizzle_mode_values swizzle,
737 switch (swizzle) {
|
| amdgpu_dcn10_hubp.c | 162 SW_MODE, info->gfx9.swizzle,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/ |
| dc_hw_types.h | 347 enum swizzle_mode_values swizzle; member in struct:dc_tiling_info::__anon788fbb990808
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| amdgpu_dce_mem_input.c | 365 GRPH_SW_MODE, info->gfx9.swizzle,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/ |
| amdgpu_dcn_calcs.c | 297 /* Unsupported swizzle modes for dcn */
336 input->src.sw_mode = pipe->plane_state->tiling_info.gfx9.swizzle;
345 input->src.macro_tile_size = swizzle_mode_to_macro_tile_size(pipe->plane_state->tiling_info.gfx9.swizzle);
984 pipe->plane_state->tiling_info.gfx9.swizzle);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/ |
| amdgpu_dm.c | 3173 input.swizzle_mode = tiling_info->gfx9.swizzle;
3310 tiling_info->gfx9.swizzle =
6355 bool swizzle = true; local in function:amdgpu_dm_commit_planes
6401 if (dc_plane && !dc_plane->tiling_info.gfx9.swizzle)
6402 swizzle = false;
6613 swizzle) {
|
| /src/sys/external/bsd/drm2/dist/drm/i915/ |
| i915_debugfs.c | 1542 static const char *swizzle_string(unsigned swizzle)
1544 switch (swizzle) {
1574 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1576 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
|
