| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/ |
| amdgpu_processpptables.c | 80 uint16_t table_offset = get_vce_table_offset(hwmgr, local
83 if (table_offset > 0)
84 return table_offset + 1;
92 uint16_t table_offset = get_vce_clock_info_array_offset(hwmgr, local
96 if (table_offset > 0) {
98 (((unsigned long) powerplay_table) + table_offset);
108 uint16_t table_offset = get_vce_clock_info_array_offset(hwmgr, local
111 if (table_offset > 0)
112 return table_offset + get_vce_clock_info_array_size(hwmgr,
121 uint16_t table_offset = get_vce_clock_voltage_limit_table_offset(hwmgr, powerplay_table) local
135 uint16_t table_offset = get_vce_clock_voltage_limit_table_offset(hwmgr, powerplay_table); local
147 uint16_t table_offset = get_vce_state_table_offset(hwmgr, powerplay_table); local
180 uint16_t table_offset = get_uvd_table_offset(hwmgr, local
191 uint16_t table_offset = get_uvd_clock_info_array_offset(hwmgr, local
210 uint16_t table_offset = get_uvd_clock_info_array_offset(hwmgr, local
247 uint16_t table_offset = get_samu_table_offset(hwmgr, local
1216 uint16_t table_offset; local
1450 uint16_t table_offset; local
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_rlc.c | 195 u32 table_offset, table_size; local
208 table_offset = le32_to_cpu(hdr->jt_offset);
216 table_offset = le32_to_cpu(hdr->jt_offset);
224 table_offset = le32_to_cpu(hdr->jt_offset);
232 table_offset = le32_to_cpu(hdr->jt_offset);
240 table_offset = le32_to_cpu(hdr->jt_offset);
246 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
|
| mmsch_v1_0.h | 54 uint32_t table_offset; member in struct:mmsch_vf_eng_init_header
|
| amdgpu_vcn_v2_5.c | 1152 header->eng[i].table_offset = header->total_size;
|
| /src/sys/dev/pci/ |
| xhci_pci.c | 174 uint32_t table_offset; local
179 table_offset = msixtbl & PCI_MSIX_TBLOFFSET_MASK;
183 sc->sc_ios = table_offset;
|
| nvme_pci.c | 200 uint32_t table_offset; local
205 table_offset = msixtbl & PCI_MSIX_TBLOFFSET_MASK;
208 sc->sc_ios = table_offset;
|
| if_ena.c | 350 bus_size_t table_offset; local
355 table_offset = msixtbl & PCI_MSIX_TBLOFFSET_MASK;
358 adapter->sc_mapsize = table_offset;
|
| /src/sys/arch/arm/cortex/ |
| gic_v2m.c | 276 uint32_t table_offset, table_size; local
296 table_offset = tbl & PCI_MSIX_TBLOFFSET_MASK;
302 BUS_SPACE_MAP_LINEAR, roundup(table_size, PAGE_SIZE), table_offset,
|
| gicv3_its.c | 642 uint32_t table_offset, table_size; local
656 table_offset = tbl & PCI_MSIX_TBLOFFSET_MASK;
662 BUS_SPACE_MAP_LINEAR, roundup(table_size, PAGE_SIZE), table_offset,
|
| /src/sys/arch/x86/pci/ |
| msipic.c | 674 uint32_t table_offset; local
708 table_offset = tbl & PCI_MSIX_TBLOFFSET_MASK;
746 roundup(table_size, PAGE_SIZE), table_offset,
766 err = _x86_memio_map(pa->pa_memt, memaddr + table_offset, bssize, flags,
|
| /src/sys/arch/arm/apple/ |
| apple_pcie.c | 627 uint32_t table_offset, table_size; local
646 table_offset = tbl & PCI_MSIX_TBLOFFSET_MASK;
652 BUS_SPACE_MAP_LINEAR, roundup(table_size, PAGE_SIZE), table_offset,
|
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_cik.c | 6443 u32 table_offset, table_size; local
6462 table_offset = le32_to_cpu(hdr->jt_offset);
6468 table_offset = le32_to_cpu(hdr->jt_offset);
6474 table_offset = le32_to_cpu(hdr->jt_offset);
6480 table_offset = le32_to_cpu(hdr->jt_offset);
6486 table_offset = le32_to_cpu(hdr->jt_offset);
6492 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
6501 table_offset = CP_ME_TABLE_OFFSET;
6504 table_offset = CP_ME_TABLE_OFFSET;
6507 table_offset = CP_ME_TABLE_OFFSET
[all...] |
