/src/sys/arch/aarch64/include/ |
frame.h | 41 uint64_t tf_esr; // 32-bit register member in struct:trapframe
|
/src/sys/arch/powerpc/booke/ |
trap.c | 129 return VM_PROT_READ | (tf->tf_esr & ESR_ST ? VM_PROT_WRITE : 0); 463 tf->tf_srr0, tf->tf_srr1, tf->tf_esr, 470 if (tf->tf_esr & ESR_PTR) { 497 if (tf->tf_esr & (ESR_PIL|ESR_PPR)) { 504 if (tf->tf_esr & ESR_PIL) { 523 if (tf->tf_esr & ESR_PIL) { 525 } else if (tf->tf_esr & ESR_PPR) { 527 } else if (tf->tf_esr & ESR_PTR) { 551 mtspr(SPR_DBSR, tf->tf_esr); 552 KASSERT(tf->tf_esr & (DBSR_IAC1|DBSR_IAC2|DBSR_BRT)) [all...] |
/src/sys/arch/powerpc/include/ |
frame.h | 114 uint32_t tf_esr; member in struct:trapframe 138 uint32_t tf_esr; member in struct:trapframe32
|
/src/sys/arch/aarch64/aarch64/ |
aarch32_syscall.c | 79 if ((tf->tf_esr & 0xffff) != SYSCALL_CODE_REG_SVC) { 93 uint32_t code = tf->tf_esr & 0xffff; /* XXX: 16-23bits are omitted */ 97 (void *)(tf->tf_pc - 2), tf->tf_esr);
|
syscall.c | 112 size_t code = tf->tf_esr & 0xffff;
|
trap.c | 200 const uint32_t esr = tf->tf_esr; 413 const uint32_t esr = tf->tf_esr; 492 eclass_trapname(eclass), tf->tf_esr, tf->tf_pc, 825 const uint32_t esr = tf->tf_esr; 906 eclass_trapname(eclass), tf->tf_esr, tf->tf_pc, 990 tf->tf_esr, tf->tf_far);
|
fault.c | 154 esr = tf->tf_esr;
|
db_trace.c | 88 (tf_buf.tf_esr == (uint64_t)-1) ? "Interrupt" : 89 eclass_trapname(__SHIFTOUT(tf_buf.tf_esr, ESR_EC)),
|
db_machdep.c | 255 tf->tf_esr, tf->tf_far); 278 tf->tf_esr, tf->tf_far); 1157 if (__SHIFTOUT(tf->tf_esr, ESR_ISS) == 0xffff)
|
/src/sys/arch/powerpc/ibm4xx/ |
trap.c | 197 if (tf->tf_esr & (ESR_DST|ESR_DIZ)) 204 (void *)va, tf->tf_esr)); 230 if (tf->tf_esr & (ESR_DST|ESR_DIZ)) 236 tf->tf_dear, tf->tf_esr)); 306 if (tf->tf_esr & ESR_PTR) { 328 } else if (tf->tf_esr & ESR_PPR) {
|
/src/sys/arch/powerpc/powerpc/ |
db_trace.c | 244 (R(&tf->tf_esr) & ESR_DST 321 (*pr)(" esr=%#x pid=%#x", R(&tf->tf_esr),
|
db_interface.c | 245 DDB_REGS->esr = tf->tf_esr; 287 tf->tf_esr = DDB_REGS->esr; 618 tf->tf_srr0, tf->tf_srr1, tf->tf_dear, tf->tf_esr);
|