| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_dpp_cm.c | 55 dpp->tf_shift->field_name, dpp->tf_mask->field_name
124 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11;
126 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12;
219 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_OCSC_C11;
221 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_OCSC_C12;
266 reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET;
268 reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
270 reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET;
272 reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
275 reg->masks.field_region_end = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_B
[all...] |
| amdgpu_dcn10_dpp.c | 54 dpp->tf_shift->field_name, dpp->tf_mask->field_name
511 if (dpp->tf_mask->DPPCLK_RATE_CONTROL)
566 const struct dcn_dpp_mask *tf_mask)
576 dpp->tf_mask = tf_mask;
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| amdgpu_dcn10_dpp_dscl.c | 55 dpp->tf_shift->field_name, dpp->tf_mask->field_name
387 scl_mode, dpp->tf_mask->SCL_COEF_RAM_SELECT_CURRENT,
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| amdgpu_dcn10_resource.c | 410 static const struct dcn_dpp_mask tf_mask = { variable in typeref:typename:const struct dcn_dpp_mask
633 &tf_regs[inst], &tf_shift, &tf_mask);
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| dcn10_dpp.h | 1351 const struct dcn_dpp_mask *tf_mask; member in struct:dcn10_dpp
1515 const struct dcn_dpp_mask *tf_mask);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_dpp_cm.c | 52 dpp->tf_shift->field_name, dpp->tf_mask->field_name
195 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11;
197 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12;
290 icsc_regs.masks.csc_c11 = dpp->tf_mask->CM_ICSC_C11;
292 icsc_regs.masks.csc_c12 = dpp->tf_mask->CM_ICSC_C12;
368 reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET;
370 reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
372 reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET;
374 reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
377 reg->masks.field_region_end = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_B
[all...] |
| amdgpu_dcn20_dpp.c | 54 dpp->tf_shift->field_name, dpp->tf_mask->field_name
498 const struct dcn2_dpp_mask *tf_mask)
508 dpp->tf_mask = tf_mask;
|
| dcn20_dpp.h | 687 const struct dcn2_dpp_mask *tf_mask; member in struct:dcn20_dpp
777 const struct dcn2_dpp_mask *tf_mask);
|
| amdgpu_dcn20_resource.c | 663 static const struct dcn2_dpp_mask tf_mask = { variable in typeref:typename:const struct dcn2_dpp_mask
986 &tf_regs[inst], &tf_shift, &tf_mask))
|
| /src/usr.sbin/npf/npfctl/ |
| npf_bpf_comp.c | 789 npfctl_bpf_tcpfl(npf_bpf_t *ctx, uint8_t tf, uint8_t tf_mask)
792 const bool usingmask = tf_mask != tf;
824 BPF_STMT(BPF_ALU+BPF_AND+BPF_K, tf_mask),
835 uint32_t mwords[] = { BM_TCPFL, 2, tf, tf_mask };
|
| npf_show.c | 261 const unsigned tf = words[0], tf_mask = words[1]; local in function:print_tcpflags
274 if (tf != tf_mask) {
276 tcpflags2string(buf + n, tf_mask);
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| npf_build.c | 385 uint8_t *tf, *tf_mask; local in function:npfctl_build_proto_block
389 tf_mask = npfvar_get_data(popts, NPFVAR_TCPFLAG, 1);
390 npfctl_bpf_tcpfl(ctx, *tf, *tf_mask);
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/ |
| amdgpu_dcn21_resource.c | 636 static const struct dcn2_dpp_mask tf_mask = { variable in typeref:typename:const struct dcn2_dpp_mask
702 &tf_regs[inst], &tf_shift, &tf_mask))
|
